mirror of https://github.com/YosysHQ/yosys.git
Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and `cellbits_to_tplbits`.
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5cb4ae4666
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6d64d768b0
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@ -862,9 +862,9 @@ struct TechmapWorker
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techmap_do_cache[new_tpl] = true;
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tpl = new_tpl;
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std::map<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
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std::map<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
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std::map<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
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dict<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
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dict<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
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dict<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
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for (auto wire : tpl->wires().to_vector())
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{
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