mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
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commit
bf7d36627e
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@ -58,7 +58,7 @@ struct ClkPartPass : public Pass {
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing CLKPART pass (TODO).\n");
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log_header(design, "Executing CLKPART pass (partition design according to clock domain).\n");
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log_push();
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clear_flags();
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@ -233,15 +233,16 @@ struct ClkPartPass : public Pass {
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std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
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std::get<2>(it.first) ? "" : "!", log_signal(std::get<3>(it.first)));
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for (auto &it : assigned_cells) {
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RTLIL::Selection sel(false);
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sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end());
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if (assigned_cells.size() > 1)
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for (auto &it : assigned_cells) {
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RTLIL::Selection sel(false);
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sel.selected_members[mod->name] = pool<IdString>(it.second.begin(), it.second.end());
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RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str());
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Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str()));
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RTLIL::IdString submod = stringf("%s.%s", mod->name.c_str(), NEW_ID.c_str());
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Pass::call_on_selection(design, sel, stringf("submod -name %s", submod.c_str()));
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design->module(submod)->set_bool_attribute(ID(clkpart));
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}
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design->module(submod)->set_bool_attribute(ID(clkpart));
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}
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}
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}
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