riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

RTLIL: factor out RTLIL::Module::addMemory. NFC.

This commit is contained in:
whitequark 2020-06-03 14:35:27 +00:00
parent ebbbe2156e
commit 9338ff66b9
4 changed files with 16 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
kernel/rtlil.cc
View File

@ -1884,6 +1884,18 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
return cell;
}
RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other)
{
RTLIL::Memory *mem = new RTLIL::Memory;
mem->name = name;
mem->width = other->width;
mem->start_offset = other->start_offset;
mem->size = other->size;
mem->attributes = other->attributes;
memories[mem->name] = mem;
return mem;
}
#define DEF_METHOD(_func, _y_size, _type) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \

2
kernel/rtlil.h
View File

@ -1170,6 +1170,8 @@ public:
RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);
// The add* methods create a cell and return the created cell. All signals must exist in advance.
RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");

8
passes/techmap/flatten.cc
View File

@ -79,15 +79,9 @@ struct FlattenWorker
for (auto &it : tpl->memories) {
IdString m_name = it.first;
apply_prefix(cell->name, m_name);
RTLIL::Memory *m = new RTLIL::Memory;
m->name = m_name;
m->width = it.second->width;
m->start_offset = it.second->start_offset;
m->size = it.second->size;
m->attributes = it.second->attributes;
RTLIL::Memory *m = module->addMemory(m_name, it.second);
if (m->attributes.count(ID::src))
m->add_strpool_attribute(ID::src, extra_src_attrs);
module->memories[m->name] = m;
memory_renames[it.first] = m->name;
design->select(module, m);
}

8
passes/techmap/techmap.cc
View File

@ -174,15 +174,9 @@ struct TechmapWorker
for (auto &it : tpl->memories) {
IdString m_name = it.first;
apply_prefix(cell->name, m_name);
RTLIL::Memory *m = new RTLIL::Memory;
m->name = m_name;
m->width = it.second->width;
m->start_offset = it.second->start_offset;
m->size = it.second->size;
m->attributes = it.second->attributes;
RTLIL::Memory *m = module->addMemory(m_name, it.second);
if (m->attributes.count(ID::src))
m->add_strpool_attribute(ID::src, extra_src_attrs);
module->memories[m->name] = m;
memory_renames[it.first] = m->name;
design->select(module, m);
}