mirror of https://github.com/YosysHQ/yosys.git
Fix submod -hidden
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435d33c373
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5e487b103c
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@ -151,15 +151,16 @@ struct SubmodWorker
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new_wire_name = stringf("%s[%d]", wire->name.c_str(), bit.offset);
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if (new_wire_port_input || new_wire_port_output) {
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if (new_wire_name[0] == '$')
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do {
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std::string next_wire_name = stringf("%s\\n%d", hidden_mode ? "$submod" : ":", auto_name_counter++);
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while (1) {
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std::string next_wire_name = stringf("%s\\n%d", hidden_mode ? "$submod" : "", auto_name_counter++);
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if (all_wire_names.count(next_wire_name) == 0) {
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all_wire_names.insert(next_wire_name);
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new_wire_name = next_wire_name;
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break;
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}
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} while (new_wire_name[0] == '$');
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else
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new_wire_name = stringf("$submod%s\n", new_wire_name.c_str());
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}
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else if (hidden_mode)
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new_wire_name = stringf("$submod%s", new_wire_name.c_str());
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}
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RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name);
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