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abc9_ops: -prep_dff_map to warn if no specify cells
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@ -206,13 +206,18 @@ void prep_dff_map(RTLIL::Design *design)
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D = w;
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}
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// Rewrite $specify cells that end with $_DFF_[NP]_.Q
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// to $_DFF_[NP]_.D since it will be moved into
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// the submodule
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for (auto cell : specify_cells) {
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auto DST = cell->getPort(ID::DST);
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DST.replace(Q, D);
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cell->setPort(ID::DST, DST);
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if (GetSize(specify_cells) == 0) {
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log_warning("Module '%s' marked (* abc9_flop *) contains no specify timing information.\n", log_id(module));
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}
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else {
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// Rewrite $specify cells that end with $_DFF_[NP]_.Q
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// to $_DFF_[NP]_.D since it will be moved into
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// the submodule
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for (auto cell : specify_cells) {
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auto DST = cell->getPort(ID::DST);
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DST.replace(Q, D);
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cell->setPort(ID::DST, DST);
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}
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}
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continue_outer_loop: ;
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}
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