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Add comments for xilinx_dsp_cascade
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Eddie Hung
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12fd2ec4f0
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792cd31052
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@ -1,3 +1,46 @@
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// This file describes the third of three pattern matcher setups that
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// forms the `xilinx_dsp` pass described in xilinx_dsp.cc
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// At a high level, it works as follows:
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// (1) Starting from a DSP48E1 cell that (a) has the Z multiplexer
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// (controlled by OPMODE[6:4]) set to zero and (b) doesn't already
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// use the 'PCOUT' port
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// (2.1) Match another DSP48E1 cell that (a) does not have the CREG enabled,
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// (b) has its Z multiplexer output set to the 'C' port, which is
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// driven by the 'P' output of the previous DSP cell, and (c) has its
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// 'PCIN' port unused
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// (2.2) Same as (2.1) but with the 'C' port driven by the 'P' output of the
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// previous DSP cell right-shifted by 17 bits
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// (3) For this subequent DSP48E1 match (i.e. PCOUT -> PCIN cascade exists)
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// if (a) the previous DSP48E1 uses either the A2REG or A1REG, (b) this
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// DSP48 does not use A2REG nor A1REG, (c) this DSP48E1 does not already
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// have an ACOUT -> ACIN cascade, (d) the previous DSP does not already
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// use its ACOUT port, then examine if an ACOUT -> ACIN cascade
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// opportunity exists by matching for a $dff-with-optional-clock-enable-
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// or-reset and checking that the 'D' input of this register is the same
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// as the 'A' input of the previous DSP
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// (4) Same as (3) but for BCOUT -> BCIN cascade
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// (5) Recursively go to (2.1) until no more matches possible, keeping track
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// of the longest possible chain found
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// (6) The longest chain is then divided into chunks of no more than
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// MAX_DSP_CASCADE in length (to prevent long cascades that exceed the
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// height of a DSP column) with each DSP in each chunk being rewritten
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// to use [ABP]COUT -> [ABP]CIN cascading as appropriate
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// Notes:
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// - Currently, [AB]COUT -> [AB]COUT cascades (3 or 4) are only considered
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// if a PCOUT -> PCIN cascade is (2.1 or 2.2) first identified; this need
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// not be the case --- [AB] cascades can exist independently of a P cascade
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// (though all three cascades must come from the same DSP). This situation
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// is not handled currently.
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// - In addition, [AB]COUT -> [AB]COUT cascades (3 or 4) are currently
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// conservative in that they examine the situation where (a) the previous
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// DSP has [AB]2REG or [AB]1REG enabled, (b) that the downstream DSP has no
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// registers enabled, and (c) that there exists only one additional register
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// between the upstream and downstream DSPs. This can certainly be relaxed
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// to identify situations ranging from (i) neither DSP uses any registers,
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// to (ii) upstream DSP has 2 registers, downstream DSP has 2 registers, and
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// there exists a further 2 registers between them. This remains a TODO
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// item.
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pattern xilinx_dsp_cascade
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udata <std::function<SigSpec(const SigSpec&)>> unextend
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@ -6,7 +49,7 @@ state <Cell*> next
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state <SigSpec> clock
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state <int> AREG BREG
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// subpattern
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// Variables used for subpatterns
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <int> ffoffset
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@ -19,12 +62,19 @@ code
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#define MAX_DSP_CASCADE 20
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endcode
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// (1) Starting from a DSP48E1 cell that (a) has the Z multiplexer
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// (controlled by OPMODE[6:4]) set to zero and (b) doesn't already
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// use the 'PCOUT' port
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match first
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select first->type.in(\DSP48E1)
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select port(first, \OPMODE, Const(0, 7)).extract(4,3) == Const::from_string("000")
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select nusers(port(first, \PCOUT, SigSpec())) <= 1
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endmatch
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// (6) The longest chain is then divided into chunks of no more than
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// MAX_DSP_CASCADE in length (to prevent long cascades that exceed the
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// height of a DSP column) with each DSP in each chunk being rewritten
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// to use [ABP]COUT -> [ABP]CIN cascading as appropriate
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code
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longest_chain.clear();
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chain.emplace_back(first, -1, -1, -1);
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@ -106,6 +156,10 @@ subpattern tail
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arg first
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arg next
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// (2.1) Match another DSP48E1 cell that (a) does not have the CREG enabled,
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// (b) has its Z multiplexer output set to the 'C' port, which is
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// driven by the 'P' output of the previous DSP cell, and (c) has its
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// 'PCIN' port unused
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match nextP
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select nextP->type.in(\DSP48E1)
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select !param(nextP, \CREG, State::S1).as_bool()
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@ -116,6 +170,8 @@ match nextP
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semioptional
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endmatch
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// (2.2) Same as (2.1) but with the 'C' port driven by the 'P' output of the
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// previous DSP cell right-shifted by 17 bits
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match nextP_shift17
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if !nextP
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select nextP_shift17->type.in(\DSP48E1)
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@ -145,6 +201,14 @@ code next
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}
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endcode
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// (3) For this subequent DSP48E1 match (i.e. PCOUT -> PCIN cascade exists)
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// if (a) the previous DSP48E1 uses either the A2REG or A1REG, (b) this
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// DSP48 does not use A2REG nor A1REG, (c) this DSP48E1 does not already
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// have an ACOUT -> ACIN cascade, (d) the previous DSP does not already
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// use its ACOUT port, then examine if an ACOUT -> ACIN cascade
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// opportunity exists by matching for a $dff-with-optional-clock-enable-
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// or-reset and checking that the 'D' input of this register is the same
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// as the 'A' input of the previous DSP
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code argQ clock AREG
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AREG = -1;
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if (next) {
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@ -152,7 +216,6 @@ code argQ clock AREG
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if (param(prev, \AREG, 2).as_int() > 0 &&
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param(next, \AREG, 2).as_int() > 0 &&
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param(next, \A_INPUT, Const("DIRECT")).decode_string() == "DIRECT" &&
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port(next, \ACIN, SigSpec()).is_fully_zero() &&
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nusers(port(prev, \ACOUT, SigSpec())) <= 1) {
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argQ = unextend(port(next, \A));
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clock = port(prev, \CLK);
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@ -174,6 +237,7 @@ reject_AREG: ;
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}
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endcode
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// (4) Same as (3) but for BCOUT -> BCIN cascade
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code argQ clock BREG
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BREG = -1;
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if (next) {
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@ -203,13 +267,14 @@ reject_BREG: ;
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}
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endcode
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// (5) Recursively go to (2.1) until no more matches possible, recording the
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// longest possible chain
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code
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if (next) {
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chain.emplace_back(next, nextP_shift17 ? 17 : nextP ? 0 : -1, AREG, BREG);
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SigSpec sigC = unextend(port(next, \C));
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// TODO: Cannot use 'reject' since semioptional
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if (nextP_shift17) {
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if (GetSize(sigC)+17 <= GetSize(port(std::get<0>(chain.back()), \P)) &&
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port(std::get<0>(chain.back()), \P).extract(17, GetSize(sigC)) != sigC)
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@ -232,22 +297,41 @@ endcode
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// #######################
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// Subpattern for matching against input registers, based on knowledge of the
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// 'Q' input.
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// At a high level:
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// (1) Starting from a $dff cell that (partially or fully) drives the given
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// 'Q' argument
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// (2) Match for a $mux cell implementing synchronous reset semantics ---
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// one that exclusively drives the 'D' input of the $dff, with one of its
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// $mux inputs being fully zero
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// (3) Match for a $mux cell implement clock enable semantics --- one that
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// exclusively drives the 'D' input of the $dff (or the other input of
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// the reset $mux) and where one of this $mux's inputs is connected to
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// the 'Q' output of the $dff
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subpattern in_dffe
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argQ.chunks()) {
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for (const auto &c : argQ.chunks()) {
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// Abandon matches when 'Q' is a constant
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if (!c.wire)
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reject;
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// Abandon matches when 'Q' has the keep attribute set
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if (c.wire->get_bool_attribute(\keep))
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reject;
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Const init = c.wire->attributes.at(\init, State::Sx);
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if (!init.is_fully_undef() && !init.is_fully_zero())
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reject;
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// Abandon matches when 'Q' has a non-zero init attribute set
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// (not supported by DSP48E1)
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Const init = c.wire->attributes.at(\init, Const());
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for (auto b : init.extract(c.offset, c.width))
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if (b != State::Sx && b != State::S0)
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reject;
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}
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endcode
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// (1) Starting from a $dff cell that (partially or fully) drives the given
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// 'Q' argument
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match ff
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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@ -260,14 +344,12 @@ match ff
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filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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filter clock == SigBit() || port(ff, \CLK) == clock
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set ffoffset offset
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endmatch
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code argQ argD
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{
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if (clock != SigBit() && port(ff, \CLK) != clock)
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reject;
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SigSpec Q = port(ff, \Q);
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dff = ff;
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dffclock = port(ff, \CLK);
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@ -279,9 +361,11 @@ code argQ argD
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// has two (ff, ffrstmux) users
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if (nusers(dffD) > 2)
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argD = SigSpec();
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}
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endcode
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// (2) Match for a $mux cell implementing synchronous reset semantics ---
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// exclusively drives the 'D' input of the $dff, with one of the $mux
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// inputs being fully zero
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match ffrstmux
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if !argD.empty()
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select ffrstmux->type.in($mux)
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@ -313,6 +397,10 @@ code argD
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dffrstmux = nullptr;
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endcode
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// (3) Match for a $mux cell implement clock enable semantics --- one that
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// exclusively drives the 'D' input of the $dff (or the other input of
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// the reset $mux) and where one of this $mux's inputs is connected to
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// the 'Q' output of the $dff
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match ffcemux
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if !argD.empty()
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select ffcemux->type.in($mux)
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