mirror of https://github.com/YosysHQ/yosys.git
Improve style in `passes/sat/qbfsat.cc`.
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1db73e8dd2
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0ca3a8e94f
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@ -227,14 +227,13 @@ void assume_miter_outputs(RTLIL::Module *module) {
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if (wires_to_assume.size() == 0)
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return;
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else {
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log("Adding $assume cell for outputs: ");
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log("Adding $assume cell for output(s): ");
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for (auto w : wires_to_assume)
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log("\"%s\" ", w->name.c_str());
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log("\n");
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}
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unsigned long i = 0;
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while (wires_to_assume.size() > 1) {
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for(auto i = 0; wires_to_assume.size() > 1; ++i) {
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std::vector<RTLIL::Wire *> buf;
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for (auto j = 0; j + 1 < GetSize(wires_to_assume); j += 2) {
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std::stringstream strstr; strstr << i << "_" << j;
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@ -245,7 +244,6 @@ void assume_miter_outputs(RTLIL::Module *module) {
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if (wires_to_assume.size() % 2 == 1)
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buf.push_back(wires_to_assume[wires_to_assume.size() - 1]);
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wires_to_assume.swap(buf);
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++i;
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}
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#ifndef NDEBUG
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