mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
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commit
588a713b54
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@ -370,7 +370,7 @@ struct XAigerWriter
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unused_bits.erase(I);
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}
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if (w->port_output)
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for (const auto &b : rhs.bits()) {
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for (const auto &b : rhs) {
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SigBit O = sigmap(b);
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if (O != b)
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alias_map[O] = b;
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@ -754,15 +754,6 @@ void reintegrate(RTLIL::Module *module)
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c.wire = module->wires_.at(remap_name(c.wire->name));
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newsig.append(c);
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}
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auto it = existing_cell->connections_.find(port_name);
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if (it == existing_cell->connections_.end())
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continue;
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if (GetSize(newsig) > GetSize(it->second))
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newsig = newsig.extract(0, GetSize(it->second));
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else
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log_assert(GetSize(newsig) == GetSize(it->second));
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cell->setPort(port_name, newsig);
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if (w->port_input && !abc9_flop)
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