mirror of https://github.com/YosysHQ/yosys.git
extract_counter: Fix outputting count to module port
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@ -99,7 +99,9 @@ struct CounterExtraction
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int count_value; //value we count from
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RTLIL::SigSpec ce; //clock signal
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RTLIL::SigSpec clk; //clock enable, if any
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RTLIL::SigSpec outsig; //counter output signal
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RTLIL::SigSpec outsig; //counter overflow output signal
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RTLIL::SigSpec poutsig; //counter parallel output signal
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bool has_pout; //whether parallel output is used
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RTLIL::Cell* count_mux; //counter mux
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RTLIL::Cell* count_reg; //counter register
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RTLIL::Cell* underflow_inv; //inverter reduction for output-underflow detect
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@ -283,6 +285,8 @@ int counter_tryextract(
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//(unless we have a parallel output!)
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//If we have a clock enable, 3 is OK
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const RTLIL::SigSpec qport = count_reg->getPort(ID(Q));
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extract.poutsig = qport;
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extract.has_pout = false;
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const RTLIL::SigSpec cnout = sigmap(qport);
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pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg);
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unsigned int max_loads = 2;
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@ -309,6 +313,7 @@ int counter_tryextract(
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//Figure out what port(s) are driven by it
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//TODO: this can probably be done more efficiently w/o multiple iterations over our whole net?
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//TODO: For what purpose do we actually need extract.pouts?
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for(auto b : qport)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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@ -317,10 +322,19 @@ int counter_tryextract(
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if(x.cell != c)
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continue;
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extract.pouts.insert(ModIndex::PortInfo(c, x.port, 0));
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extract.has_pout = true;
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}
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}
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}
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}
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for (auto b : qport)
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{
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if(index.query_is_output(b))
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{
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// Parallel out goes out of module
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extract.has_pout = true;
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}
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}
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if(!is_full_bus(cnout, index, count_reg, ID(Q), underflow_inv, ID::A, true))
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return 18;
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if(!is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::A, true))
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@ -508,13 +522,11 @@ void counter_worker(
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for(auto load : extract.pouts)
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{
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log(" Counter has parallel output to cell %s port %s\n", log_id(load.cell->name), log_id(load.port));
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//Find the wire hooked to the old port
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auto sig = load.cell->getPort(load.port);
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}
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if(extract.has_pout)
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{
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//Connect it to our parallel output
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//(this is OK to do more than once b/c they all go to the same place)
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cell->setPort(ID(POUT), sig);
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cell->setPort(ID(POUT), extract.poutsig);
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cell->setParam(ID(HAS_POUT), RTLIL::Const(1));
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}
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@ -546,7 +558,7 @@ void counter_worker(
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//Optimize the counter
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//If we have no parallel output, and we have redundant bits, shrink us
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if(extract.pouts.empty())
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if(!extract.has_pout)
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{
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//TODO: Need to update this when we add support for counters with nonzero reset values
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//to make sure the reset value fits in our bit space too
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