riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

abc9_ops: cleanup

This commit is contained in:
Eddie Hung 2020-01-14 13:13:15 -08:00
parent 300003cb78
commit 593897ffc0
1 changed files with 5 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
passes/techmap/abc9_ops.cc
View File

@ -233,25 +233,15 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
auto w = inst_module->wire(port_name);
log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) {
if (w->port_input) {
if (carry_in != IdString())
log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(inst_module));
log_assert(w->port_input != w->port_output);
if (w->port_input)
carry_in = port_name;
}
if (w->port_output) {
if (carry_out != IdString())
log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(inst_module));
else if (w->port_output)
carry_out = port_name;
}
}
else
r.first->second.push_back(port_name);
}
if (carry_in != IdString() && carry_out == IdString())
log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(inst_module));
if (carry_in == IdString() && carry_out != IdString())
log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(inst_module));
if (carry_in != IdString()) {
r.first->second.push_back(carry_in);
r.first->second.push_back(carry_out);
@ -723,9 +713,10 @@ void reintegrate(RTLIL::Module *module)
auto w = box_module->wire(port_name);
log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) {
log_assert(w->port_input != w->port_output);
if (w->port_input)
carry_in = port_name;
if (w->port_output)
else if (w->port_output)
carry_out = port_name;
}
else