mirror of https://github.com/YosysHQ/yosys.git
abc9: cleanup
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886c5c5883
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1cf974ff40
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@ -249,7 +249,7 @@ struct abc9_output_filter
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};
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void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
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bool cleanup, vector<int> lut_costs, bool dff, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
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bool cleanup, vector<int> lut_costs, bool dff_mode, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
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bool show_tempdir, std::string box_file, std::string lut_file,
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std::string wire_delay, bool nomfs
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)
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@ -420,7 +420,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
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dict<IdString, bool> abc9_box;
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vector<RTLIL::Cell*> boxes;
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for (auto cell : module->selected_cells()) {
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) {
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module->remove(cell);
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continue;
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@ -431,7 +431,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
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jt = abc9_box.insert(std::make_pair(cell->type, box_module && box_module->attributes.count(ID(abc9_box_id)))).first;
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if (jt->second) {
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if (box_module->get_bool_attribute("\\abc9_flop")) {
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if (dff)
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if (dff_mode)
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boxes.emplace_back(cell);
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else
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box_module->set_bool_attribute("\\abc9_keep", false);
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@ -843,7 +843,7 @@ struct Abc9Pass : public Pass {
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#endif
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std::string script_file, clk_str, box_file, lut_file;
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std::string delay_target, lutin_shared = "-S 1", wire_delay;
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bool fast_mode = false, dff = false, cleanup = true;
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bool fast_mode = false, dff_mode = false, cleanup = true;
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bool show_tempdir = false;
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bool nomfs = false;
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vector<int> lut_costs;
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@ -921,7 +921,7 @@ struct Abc9Pass : public Pass {
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continue;
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}
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if (arg == "-dff") {
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dff = true;
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dff_mode = true;
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continue;
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}
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if (arg == "-nocleanup") {
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@ -1010,21 +1010,22 @@ struct Abc9Pass : public Pass {
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CellTypes ct(design);
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for (auto module : design->selected_modules())
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{
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if (module->attributes.count(ID(abc9_box_id)))
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continue;
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if (module->processes.size() > 0) {
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log("Skipping module %s as it contains processes.\n", log_id(module));
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continue;
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}
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log_assert(!module->attributes.count(ID(abc9_box_id)));
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if (!design->selected_whole_module(module))
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log_cmd_error("Can't handle partially selected module %s!\n", log_id(module));
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assign_map.set(module);
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typedef SigSpec clkdomain_t;
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dict<clkdomain_t, int> clk_to_mergeability;
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if (dff)
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for (auto cell : module->selected_cells()) {
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if (dff_mode)
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for (auto cell : module->cells()) {
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if (cell->type != "$__ABC9_FF_")
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continue;
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@ -1050,7 +1051,7 @@ struct Abc9Pass : public Pass {
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log_assert(r2.second);
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}
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else
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for (auto cell : module->selected_cells()) {
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for (auto cell : module->cells()) {
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auto inst_module = design->module(cell->type);
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if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop"))
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continue;
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@ -1058,7 +1059,7 @@ struct Abc9Pass : public Pass {
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}
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design->selected_active_module = module->name.str();
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abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, dff,
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abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, dff_mode,
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delay_target, lutin_shared, fast_mode, show_tempdir,
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box_file, lut_file, wire_delay, nomfs);
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design->selected_active_module.clear();
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