mirror of https://github.com/YosysHQ/yosys.git
opt_expr: const_xnor replacement to pad Y with 1'b1
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@ -575,7 +575,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (cell->type.in(ID($xnor), ID($_XNOR_))) {
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cover("opt.opt_expr.const_xnor");
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// For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_
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replace_cell(assign_map, module, cell, "const_xnor", ID::Y, RTLIL::State::S1);
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int width = cell->getParam(ID::Y_WIDTH).as_int();
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replace_cell(assign_map, module, cell, "const_xnor", ID::Y, SigSpec(RTLIL::State::S1, width));
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goto next_cell;
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}
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log_abort();
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@ -83,3 +83,49 @@ miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3
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sat -verify -prove-asserts -show-ports -enable_undef miter3
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miter -equiv -flatten -make_assert -make_outputs coarse_keepdc fine_keepdc miter4
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sat -verify -prove-asserts -show-ports -enable_undef miter4
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# Single-bit $xnor extension
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design -reset
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read_verilog -noopt <<EOT
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module gold(input i, output [1:0] o, p, q);
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assign o = i ~^ i;
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assign p = 1'b0 ~^ i;
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assign q = 1'b1 ~^ i;
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endmodule
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EOT
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select -assert-count 3 t:$xnor
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copy gold coarse
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copy gold fine
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copy gold coarse_keepdc
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copy gold fine_keepdc
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cd coarse
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opt_expr -fine
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select -assert-none t:$xnor
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cd fine
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simplemap
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opt_expr
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select -assert-none t:$_XNOR_
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x gold coarse miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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miter -equiv -flatten -make_assert -make_outputs coarse fine miter2
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sat -verify -prove-asserts -show-ports -enable_undef miter2
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cd coarse_keepdc
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opt_expr -keepdc -fine
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select -assert-count 1 t:$xnor
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cd fine_keepdc
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simplemap
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opt_expr -keepdc
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select -assert-count 0 c:$_XNOR_
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cd
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miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3
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sat -verify -prove-asserts -show-ports -enable_undef miter3
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miter -equiv -flatten -make_assert -make_outputs coarse_keepdc fine_keepdc miter4
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sat -verify -prove-asserts -show-ports -enable_undef miter4
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