diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 38dc09af5..d895fc691 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -575,7 +575,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (cell->type.in(ID($xnor), ID($_XNOR_))) { cover("opt.opt_expr.const_xnor"); // For consistency since simplemap does $xnor -> $_XOR_ + $_NOT_ - replace_cell(assign_map, module, cell, "const_xnor", ID::Y, RTLIL::State::S1); + int width = cell->getParam(ID::Y_WIDTH).as_int(); + replace_cell(assign_map, module, cell, "const_xnor", ID::Y, SigSpec(RTLIL::State::S1, width)); goto next_cell; } log_abort(); diff --git a/tests/opt/opt_expr_xnor.ys b/tests/opt/opt_expr_xnor.ys index 0f9463379..f8ef0d352 100644 --- a/tests/opt/opt_expr_xnor.ys +++ b/tests/opt/opt_expr_xnor.ys @@ -83,3 +83,49 @@ miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3 sat -verify -prove-asserts -show-ports -enable_undef miter3 miter -equiv -flatten -make_assert -make_outputs coarse_keepdc fine_keepdc miter4 sat -verify -prove-asserts -show-ports -enable_undef miter4 + + +# Single-bit $xnor extension +design -reset +read_verilog -noopt <