riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattr

This commit is contained in:
Eddie Hung 2019-12-16 12:07:49 -08:00
parent 6d4b6b1e69 87e21b0122
commit 952d62991f
4 changed files with 238 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

91
passes/memory/memory_bram.cc
View File

@ -134,6 +134,9 @@ struct rules_t
dict<string, int> min_limits, max_limits;
bool or_next_if_better, make_transp, make_outreg;
char shuffle_enable;
dict<IdString, vector<pair<IdString, Const>>> attr_match;
pair<IdString, Const> attr_val;
dict<IdString, Const> attr_unmatch;
};
dict<IdString, vector<bram_t>> brams;
@ -327,6 +330,32 @@ struct rules_t
continue;
}
if (GetSize(tokens) >= 2 && tokens[0] == "attribute") {
if (GetSize(tokens) <=2) {
size_t notval = tokens[1].find("!");
size_t val = tokens[1].find("=");
if (notval != std::string::npos) {
if (val != std::string::npos)
data.attr_unmatch[RTLIL::escape_id(tokens[1].substr(1, val-1))] = tokens[1].substr(val+1);
else
data.attr_unmatch[RTLIL::escape_id(tokens[1].substr(notval+1))] = RTLIL::Const('1');
}
continue;
}
else if (GetSize(tokens) > 2) {
for (int idx=1; idx<= GetSize(tokens)-1; idx++) {
size_t val = tokens[idx].find("=");
if (val != std::string::npos) {
data.attr_val = make_pair(RTLIL::escape_id(tokens[idx].substr(0, val)), tokens[idx].substr(val+1));
data.attr_match[RTLIL::escape_id(tokens[0])].push_back(data.attr_val);
}
}
continue;
}
}
syntax_error();
}
}
@ -724,7 +753,7 @@ grow_read_ports:;
if (match.make_transp && wr_ports <= 1) {
pi.make_transp = true;
if (pi.clocks != 0) {
if (wr_ports == 1 && wr_clkdom != clkdom) {
if (wr_ports == 1 && wr_clkdom != clkdom) {
log(" Bram port %c%d.%d cannot have soft transparency logic added as read and write clock domains differ.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
goto skip_bram_rport;
}
@ -792,6 +821,27 @@ grow_read_ports:;
log(" Updated properties: dups=%d waste=%d efficiency=%d\n",
match_properties["dups"], match_properties["waste"], match_properties["efficiency"]);
for (auto iter: match.attr_match) {
for (auto iter: iter.second) {
auto it = cell->attributes.find(iter.first);
if (iter.second.empty()) {
log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n",
log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str());
return false;
}
if (it != cell->attributes.end()) {
if (it->second == iter.second)
continue;
log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n",
log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str());
return false;
}
return true;
}
}
for (auto it : match.min_limits) {
if (!match_properties.count(it.first))
log_error("Unknown property '%s' in match rule for bram type %s.\n",
@ -1074,6 +1124,39 @@ void handle_cell(Cell *cell, const rules_t &rules)
goto next_match_rule;
}
for (auto iter: match.attr_match) {
for (auto iter: iter.second) {
auto it = cell->attributes.find(iter.first);
if (it != cell->attributes.end()) {
if (!it->second.empty()) {
if (it->second.decode_string().length() == 1)
it->second = it->second.as_string().back();
if (!it->second.decode_string().compare(iter.second.decode_string()))
goto attribute_matched;
else
log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n",
log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str());
}
}
}
}
for (auto& iter: match.attr_unmatch) {
auto it = cell->attributes.find(iter.first);
if (it != cell->attributes.end()) {
if (!it->second.empty()) {
if (it->second.decode_string().length() == 1)
it->second = it->second.as_string().back();
if (!it->second.decode_string().compare(iter.second.decode_string()))
goto next_match_rule;
log(" Rule for bram type %s is rejected: requirement 'attribute %s=\"%s\"' not met.\n",
log_id(match.name), log_id(iter.first), iter.second.decode_string().c_str());
}
}
}
for (auto it : match.min_limits) {
if (it.first == "waste" || it.first == "dups" || it.first == "acells" || it.first == "dcells" || it.first == "cells")
continue;
@ -1100,6 +1183,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
goto next_match_rule;
}
attribute_matched:
log(" Rule #%d for bram type %s (variant %d) accepted.\n", i+1, log_id(bram.name), bram.variant);
if (or_next_if_better || !best_rule_cache.empty())
@ -1225,6 +1309,11 @@ struct MemoryBramPass : public Pass {
log(" dcells ....... number of cells in 'data-direction'\n");
log(" cells ........ total number of cells (acells*dcells*dups)\n");
log("\n");
log("A match containing the condition 'attribute' followed by a name and optional\n");
log("value requires that the memory contains the given attribute name and value\n");
log("(if specified) or that the attribute is not present (prepending a '!')\n");
log("or the value is empty (if value is not specified\n).");
log("\n");
log("The interface for the created bram instances is derived from the bram\n");
log("description. Use 'techmap' to convert the created bram instances into\n");
log("instances of the actual bram cells of your target architecture.\n");

13
techlibs/xilinx/xc7_xcu_brams.txt
View File

@ -77,6 +77,9 @@ endbram
# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf
match $__XILINX_RAMB36_SDP
attribute ram_style=block ram_block=1
attribute !ram_style
attribute !logic_block
min bits 1024
min efficiency 5
shuffle_enable B
@ -85,6 +88,9 @@ match $__XILINX_RAMB36_SDP
endmatch
match $__XILINX_RAMB18_SDP
attribute ram_style=block ram_block=1
attribute !ram_style
attribute !logic_block
min bits 1024
min efficiency 5
shuffle_enable B
@ -93,6 +99,9 @@ match $__XILINX_RAMB18_SDP
endmatch
match $__XILINX_RAMB36_TDP
attribute ram_style=block ram_block=1
attribute !ram_style
attribute !logic_block
min bits 1024
min efficiency 5
shuffle_enable B
@ -101,8 +110,12 @@ match $__XILINX_RAMB36_TDP
endmatch
match $__XILINX_RAMB18_TDP
attribute ram_style=block ram_block=1
attribute !ram_style
attribute !logic_block
min bits 1024
min efficiency 5
shuffle_enable B
make_transp
endmatch

88
tests/arch/common/memory_attributes/attributes_test.v Normal file
View File

@ -0,0 +1,88 @@
`default_nettype none
module block_ram #(parameter DATA_WIDTH=4, ADDRESS_WIDTH=10)
(input wire write_enable, clk,
input wire [DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [DATA_WIDTH-1:0] data_out);
localparam WORD = (DATA_WIDTH-1);
localparam DEPTH = (2**ADDRESS_WIDTH-1);
reg [WORD:0] data_out_r;
reg [WORD:0] memory [0:DEPTH];
always @(posedge clk) begin
if (write_enable)
memory[address_in] <= data_in;
data_out_r <= memory[address_in];
end
assign data_out = data_out_r;
endmodule // block_ram
`default_nettype none
module distributed_ram #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
(input wire write_enable, clk,
input wire [DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [DATA_WIDTH-1:0] data_out);
localparam WORD = (DATA_WIDTH-1);
localparam DEPTH = (2**ADDRESS_WIDTH-1);
reg [WORD:0] data_out_r;
reg [WORD:0] memory [0:DEPTH];
always @(posedge clk) begin
if (write_enable)
memory[address_in] <= data_in;
data_out_r <= memory[address_in];
end
assign data_out = data_out_r;
endmodule // distributed_ram
`default_nettype none
module distributed_ram_manual #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
(input wire write_enable, clk,
input wire [DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [DATA_WIDTH-1:0] data_out);
localparam WORD = (DATA_WIDTH-1);
localparam DEPTH = (2**ADDRESS_WIDTH-1);
reg [WORD:0] data_out_r;
(* ram_style = "block" *) reg [WORD:0] memory [0:DEPTH];
always @(posedge clk) begin
if (write_enable)
memory[address_in] <= data_in;
data_out_r <= memory[address_in];
end
assign data_out = data_out_r;
endmodule // distributed_ram
`default_nettype none
module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4)
(input wire write_enable, clk,
input wire [DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [DATA_WIDTH-1:0] data_out);
localparam WORD = (DATA_WIDTH-1);
localparam DEPTH = (2**ADDRESS_WIDTH-1);
reg [WORD:0] data_out_r;
(* synthesis, ram_block *) reg [WORD:0] memory [0:DEPTH];
always @(posedge clk) begin
if (write_enable)
memory[address_in] <= data_in;
data_out_r <= memory[address_in];
end
assign data_out = data_out_r;
endmodule // distributed_ram

47
tests/arch/xilinx/attributes_test.ys Normal file
View File

@ -0,0 +1,47 @@
# Check that blockram memory without parameters is not modified
read_verilog ../common/memory_attributes/attributes_test.v
hierarchy -top block_ram
synth_xilinx -top block_ram
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 1 t:RAMB18E1
# Check that distributed memory without parameters is not modified
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
hierarchy -top distributed_ram
synth_xilinx -top distributed_ram
cd distributed_ram # Constrain all select calls below inside the top module
select -assert-count 8 t:RAM32X1D
# Set ram_style distributed to blockram memory; will be implemented as distributed
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
prep
setattr -mod -set ram_style "distributed" block_ram
synth_xilinx -top block_ram
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 32 t:RAM128X1D
# Set synthesis, logic_block to blockram memory; will be implemented as distributed
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
prep
setattr -mod -set logic_block 1 block_ram
synth_xilinx -top block_ram
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 0 t:RAMB18E1
select -assert-count 32 t:RAM128X1D
# Set ram_style block to a distributed memory; will be implemented as blockram
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
synth_xilinx -top distributed_ram_manual
cd distributed_ram_manual # Constrain all select calls below inside the top module
select -assert-count 1 t:RAMB18E1
# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
synth_xilinx -top distributed_ram_manual_syn
cd distributed_ram_manual_syn # Constrain all select calls below inside the top module
select -assert-count 1 t:RAMB18E1