mirror of https://github.com/YosysHQ/yosys.git
endomain -> ctrldomain
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@ -1108,8 +1108,8 @@ struct Abc9Pass : public Pass {
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std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
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std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
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typedef std::pair<IdString, SigSpec> endomain_t;
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std::map<endomain_t, int> mergeability_class;
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typedef std::pair<IdString, SigSpec> ctrldomain_t;
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std::map<ctrldomain_t, int> mergeability_class;
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for (auto cell : all_cells) {
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for (auto &conn : cell->connections())
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@ -1149,7 +1149,7 @@ struct Abc9Pass : public Pass {
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assigned_cells[abc9_clock].insert(cell->name);
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assigned_cells_reverse[cell] = abc9_clock;
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endomain_t key(cell->type, abc9_control);
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ctrldomain_t key(cell->type, abc9_control);
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auto r = mergeability_class.emplace(key, mergeability_class.size() + 1);
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auto YS_ATTRIBUTE(unused) r2 = cell->attributes.insert(std::make_pair(ID(abc9_mergeability), r.first->second));
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log_assert(r2.second);
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