mirror of https://github.com/YosysHQ/yosys.git
attributes.count() -> get_bool_attribute()
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@ -284,7 +284,7 @@ struct XAigerWriter
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toposort.node(cell->name);
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if (inst_module->attributes.count("\\abc9_flop"))
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if (inst_module->get_bool_attribute("\\abc9_flop"))
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flop_boxes.push_back(cell);
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continue;
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}
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@ -533,7 +533,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
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}
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RTLIL::Module* box_module = design->module(mapped_cell->type);
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auto abc9_flop = box_module && box_module->attributes.count("\\abc9_flop");
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auto abc9_flop = box_module && box_module->get_bool_attribute("\\abc9_flop");
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for (auto &conn : mapped_cell->connections()) {
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RTLIL::SigSpec newsig;
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for (auto c : conn.second.chunks()) {
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@ -988,7 +988,7 @@ struct Abc9Pass : public Pass {
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for (auto cell : all_cells) {
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auto inst_module = design->module(cell->type);
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if (!inst_module || !inst_module->attributes.count("\\abc9_flop")
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if (!inst_module || !inst_module->get_bool_attribute("\\abc9_flop")
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|| cell->get_bool_attribute("\\abc9_keep"))
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continue;
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