riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

cutpoint: Improve efficiency by iterating over module ports instead of module wires.

This commit is contained in:
Alberto Gonzalez 2020-06-18 17:42:36 +00:00
parent dfde1cf1c5
commit 76dfa81790
No known key found for this signature in database
GPG Key ID: 8395A8BA109708B2
1 changed files with 10 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
passes/sat/cutpoint.cc
View File

@ -126,15 +126,16 @@ struct CutpointPass : public Pass {
}
vector<Wire*> rewrite_wires;
for (auto wire : module->wires()) {
if (!wire->port_input)
continue;
int bit_count = 0;
for (auto &bit : sigmap(wire))
if (cutpoint_bits.count(bit))
bit_count++;
if (bit_count)
rewrite_wires.push_back(wire);
for (auto id : module->ports) {
RTLIL::Wire *wire = module->wire(id);
if (wire->port_input) {
int bit_count = 0;
for (auto &bit : sigmap(wire))
if (cutpoint_bits.count(bit))
bit_count++;
if (bit_count)
rewrite_wires.push_back(wire);
}
}
for (auto wire : rewrite_wires) {