mirror of https://github.com/YosysHQ/yosys.git
techmap: sort celltypeMap as it determines techmap order
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@ -1313,11 +1313,13 @@ struct TechmapPass : public Pass {
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celltypeMap[RTLIL::escape_id(q)].insert(module->name);
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free(p);
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} else {
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std::string module_name = module->name.begins_with("\\$") ?
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IdString module_name = module->name.begins_with("\\$") ?
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module->name.substr(1) : module->name.str();
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celltypeMap[module_name].insert(module->name);
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}
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}
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for (auto &i : celltypeMap)
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i.second.sort(RTLIL::sort_by_id_str());
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for (auto module : design->modules())
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worker.module_queue.insert(module);
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@ -1389,6 +1391,8 @@ struct FlattenPass : public Pass {
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dict<IdString, pool<IdString>> celltypeMap;
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for (auto module : design->modules())
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celltypeMap[module->name].insert(module->name);
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for (auto &i : celltypeMap)
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i.second.sort(RTLIL::sort_by_id_str());
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RTLIL::Module *top_mod = nullptr;
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if (design->full_selection())
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