mirror of https://github.com/YosysHQ/yosys.git
Rename abc9.cc -> abc9_techmap.cc
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9e6632c40a
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@ -8,6 +8,7 @@ OBJS += passes/techmap/libparse.o
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ifeq ($(ENABLE_ABC),1)
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OBJS += passes/techmap/abc.o
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OBJS += passes/techmap/abc9.o
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OBJS += passes/techmap/abc9_techmap.o
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ifneq ($(ABCEXTERNAL),)
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passes/techmap/abc.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
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passes/techmap/abc9.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
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@ -430,7 +430,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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design->selection_stack.pop_back();
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log_header(design, "Executing ABC9.\n");
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log_header(design, "Executing ABC9_MAP.\n");
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if (!lut_costs.empty()) {
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buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str());
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@ -812,13 +812,13 @@ clone_lut:
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log_pop();
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}
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struct Abc9Pass : public Pass {
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Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { }
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struct Abc9TechmapPass : public Pass {
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Abc9TechmapPass() : Pass("abc9_map", "use ABC9 for technology mapping") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" abc9 [options] [selection]\n");
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log(" abc9_map [options] [selection]\n");
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log("\n");
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log("This pass uses the ABC tool [1] for technology mapping of yosys's internal gate\n");
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log("library to a target architecture.\n");
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@ -1305,6 +1305,6 @@ struct Abc9Pass : public Pass {
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log_pop();
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}
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} Abc9Pass;
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} Abc9TechmapPass;
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PRIVATE_NAMESPACE_END
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