mirror of https://github.com/YosysHQ/yosys.git
abc9: remove -nomfs option
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@ -250,7 +250,7 @@ struct abc9_output_filter
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void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string script_file, std::string exe_file,
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bool cleanup, vector<int> lut_costs, bool dff_mode, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
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bool show_tempdir, std::string box_file, std::string lut_file,
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std::string wire_delay, bool nomfs
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std::string wire_delay
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)
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{
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map_autoidx = autoidx++;
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@ -305,10 +305,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
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for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos))
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abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3);
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if (nomfs)
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for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
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abc9_script = abc9_script.erase(pos, strlen("&mfs"));
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abc9_script += stringf("; &write -n %s/output.aig", tempdir_name.c_str());
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abc9_script = add_echos_to_abc9_cmd(abc9_script);
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@ -833,7 +829,6 @@ struct Abc9Pass : public Pass {
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std::string delay_target, lutin_shared = "-S 1", wire_delay;
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bool fast_mode = false, dff_mode = false, cleanup = true;
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bool show_tempdir = false;
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bool nomfs = false;
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vector<int> lut_costs;
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#if 0
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@ -865,7 +860,6 @@ struct Abc9Pass : public Pass {
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if (design->scratchpad.count("abc9.W")) {
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wire_delay = "-W " + design->scratchpad_get_string("abc9.W");
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}
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nomfs = design->scratchpad_get_bool("abc9.nomfs", nomfs);
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size_t argidx;
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char pwd [PATH_MAX];
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@ -926,10 +920,6 @@ struct Abc9Pass : public Pass {
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wire_delay = "-W " + args[++argidx];
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continue;
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}
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if (arg == "-nomfs") {
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nomfs = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -1043,7 +1033,7 @@ struct Abc9Pass : public Pass {
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design->selected_active_module = module->name.str();
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abc9_module(design, module, script_file, exe_file, cleanup, lut_costs, dff_mode,
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delay_target, lutin_shared, fast_mode, show_tempdir,
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box_file, lut_file, wire_delay, nomfs);
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box_file, lut_file, wire_delay);
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design->selected_active_module.clear();
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}
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