mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs
This commit is contained in:
commit
93e680b7d3
2
Makefile
2
Makefile
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@ -115,7 +115,7 @@ LDFLAGS += -rdynamic
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LDLIBS += -lrt
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endif
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YOSYS_VER := 0.9+932
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YOSYS_VER := 0.9+1706
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GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
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OBJS = kernel/version_$(GIT_REV).o
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@ -114,20 +114,35 @@ void Pass::run_register()
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void Pass::init_register()
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{
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vector<Pass*> added_passes;
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while (first_queued_pass) {
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added_passes.push_back(first_queued_pass);
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first_queued_pass->run_register();
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first_queued_pass = first_queued_pass->next_queued_pass;
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}
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for (auto added_pass : added_passes)
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added_pass->on_register();
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}
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void Pass::done_register()
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{
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for (auto &it : pass_register)
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it.second->on_shutdown();
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frontend_register.clear();
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pass_register.clear();
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backend_register.clear();
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log_assert(first_queued_pass == NULL);
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}
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void Pass::on_register()
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{
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}
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void Pass::on_shutdown()
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{
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}
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Pass::~Pass()
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{
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}
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@ -62,6 +62,9 @@ struct Pass
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virtual void run_register();
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static void init_register();
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static void done_register();
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virtual void on_register();
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virtual void on_shutdown();
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};
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struct ScriptPass : Pass
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@ -544,6 +544,8 @@ void yosys_shutdown()
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already_shutdown = true;
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log_pop();
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Pass::done_register();
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delete yosys_design;
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yosys_design = NULL;
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@ -553,7 +555,6 @@ void yosys_shutdown()
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log_errfile = NULL;
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log_files.clear();
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Pass::done_register();
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yosys_celltypes.clear();
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#ifdef YOSYS_ENABLE_TCL
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@ -301,41 +301,40 @@ struct SccPass : public Pass {
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RTLIL::Selection newSelection(false);
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int scc_counter = 0;
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for (auto &mod_it : design->modules_)
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if (design->selected(mod_it.second))
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for (auto mod : design->selected_modules())
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{
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SccWorker worker(design, mod, nofeedbackMode, allCellTypes, maxDepth);
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if (!setAttr.empty())
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{
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SccWorker worker(design, mod_it.second, nofeedbackMode, allCellTypes, maxDepth);
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if (!setAttr.empty())
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for (const auto &cells : worker.sccList)
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{
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for (const auto &cells : worker.sccList)
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for (auto attr : setAttr)
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{
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for (auto attr : setAttr)
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{
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IdString attr_name(RTLIL::escape_id(attr.first));
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string attr_valstr = attr.second;
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string index = stringf("%d", scc_counter);
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IdString attr_name(RTLIL::escape_id(attr.first));
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string attr_valstr = attr.second;
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string index = stringf("%d", scc_counter);
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for (size_t pos = 0; (pos = attr_valstr.find("{}", pos)) != string::npos; pos += index.size())
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attr_valstr.replace(pos, 2, index);
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for (size_t pos = 0; (pos = attr_valstr.find("{}", pos)) != string::npos; pos += index.size())
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attr_valstr.replace(pos, 2, index);
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Const attr_value(attr_valstr);
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Const attr_value(attr_valstr);
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for (auto cell : cells)
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cell->attributes[attr_name] = attr_value;
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}
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scc_counter++;
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for (auto cell : cells)
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cell->attributes[attr_name] = attr_value;
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}
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}
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else
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{
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scc_counter += GetSize(worker.sccList);
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}
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if (selectMode)
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worker.select(newSelection);
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scc_counter++;
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}
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}
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else
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{
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scc_counter += GetSize(worker.sccList);
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}
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if (selectMode)
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worker.select(newSelection);
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}
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if (expect >= 0) {
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if (scc_counter == expect)
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@ -416,13 +416,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
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dict<IdString, bool> abc9_box;
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vector<RTLIL::Cell*> boxes;
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for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
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auto cell = it->second;
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for (auto cell : module->cells().to_vector()) {
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if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) {
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it = module->cells_.erase(it);
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module->remove(cell);
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continue;
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}
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++it;
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RTLIL::Module* box_module = design->module(cell->type);
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auto jt = abc9_box.find(cell->type);
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if (jt == abc9_box.end())
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