Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs

This commit is contained in:
Eddie Hung 2020-01-11 07:59:56 -08:00
commit 93e680b7d3
6 changed files with 48 additions and 32 deletions

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@ -115,7 +115,7 @@ LDFLAGS += -rdynamic
LDLIBS += -lrt
endif
YOSYS_VER := 0.9+932
YOSYS_VER := 0.9+1706
GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
OBJS = kernel/version_$(GIT_REV).o

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@ -114,20 +114,35 @@ void Pass::run_register()
void Pass::init_register()
{
vector<Pass*> added_passes;
while (first_queued_pass) {
added_passes.push_back(first_queued_pass);
first_queued_pass->run_register();
first_queued_pass = first_queued_pass->next_queued_pass;
}
for (auto added_pass : added_passes)
added_pass->on_register();
}
void Pass::done_register()
{
for (auto &it : pass_register)
it.second->on_shutdown();
frontend_register.clear();
pass_register.clear();
backend_register.clear();
log_assert(first_queued_pass == NULL);
}
void Pass::on_register()
{
}
void Pass::on_shutdown()
{
}
Pass::~Pass()
{
}

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@ -62,6 +62,9 @@ struct Pass
virtual void run_register();
static void init_register();
static void done_register();
virtual void on_register();
virtual void on_shutdown();
};
struct ScriptPass : Pass

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@ -544,6 +544,8 @@ void yosys_shutdown()
already_shutdown = true;
log_pop();
Pass::done_register();
delete yosys_design;
yosys_design = NULL;
@ -553,7 +555,6 @@ void yosys_shutdown()
log_errfile = NULL;
log_files.clear();
Pass::done_register();
yosys_celltypes.clear();
#ifdef YOSYS_ENABLE_TCL

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@ -301,41 +301,40 @@ struct SccPass : public Pass {
RTLIL::Selection newSelection(false);
int scc_counter = 0;
for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto mod : design->selected_modules())
{
SccWorker worker(design, mod, nofeedbackMode, allCellTypes, maxDepth);
if (!setAttr.empty())
{
SccWorker worker(design, mod_it.second, nofeedbackMode, allCellTypes, maxDepth);
if (!setAttr.empty())
for (const auto &cells : worker.sccList)
{
for (const auto &cells : worker.sccList)
for (auto attr : setAttr)
{
for (auto attr : setAttr)
{
IdString attr_name(RTLIL::escape_id(attr.first));
string attr_valstr = attr.second;
string index = stringf("%d", scc_counter);
IdString attr_name(RTLIL::escape_id(attr.first));
string attr_valstr = attr.second;
string index = stringf("%d", scc_counter);
for (size_t pos = 0; (pos = attr_valstr.find("{}", pos)) != string::npos; pos += index.size())
attr_valstr.replace(pos, 2, index);
for (size_t pos = 0; (pos = attr_valstr.find("{}", pos)) != string::npos; pos += index.size())
attr_valstr.replace(pos, 2, index);
Const attr_value(attr_valstr);
Const attr_value(attr_valstr);
for (auto cell : cells)
cell->attributes[attr_name] = attr_value;
}
scc_counter++;
for (auto cell : cells)
cell->attributes[attr_name] = attr_value;
}
}
else
{
scc_counter += GetSize(worker.sccList);
}
if (selectMode)
worker.select(newSelection);
scc_counter++;
}
}
else
{
scc_counter += GetSize(worker.sccList);
}
if (selectMode)
worker.select(newSelection);
}
if (expect >= 0) {
if (scc_counter == expect)

View File

@ -416,13 +416,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
dict<IdString, bool> abc9_box;
vector<RTLIL::Cell*> boxes;
for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
auto cell = it->second;
for (auto cell : module->cells().to_vector()) {
if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) {
it = module->cells_.erase(it);
module->remove(cell);
continue;
}
++it;
RTLIL::Module* box_module = design->module(cell->type);
auto jt = abc9_box.find(cell->type);
if (jt == abc9_box.end())