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abc9_ops: assert on $specify2 properties
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@ -572,7 +572,10 @@ void prep_lut(RTLIL::Design *design, int maxlut)
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continue;
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log_assert(cell->getParam(ID(SRC_WIDTH)) == 1);
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log_assert(cell->getParam(ID(DST_WIDTH)) == 1);
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SigBit s = cell->getPort(ID(SRC));
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SigBit d = cell->getPort(ID(DST));
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log_assert(s.wire->port_input);
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log_assert(d.wire->port_output);
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if (o == SigBit())
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o = d;
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else
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