mirror of https://github.com/YosysHQ/yosys.git
flatten: simplify. NFC.
Flatten is non-recursive and doesn't need to keep track of handled cells.
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@ -249,7 +249,7 @@ struct FlattenWorker
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}
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}
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bool flatten_module(RTLIL::Design *design, RTLIL::Module *module, pool<RTLIL::Cell*> &handled_cells)
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bool flatten_module(RTLIL::Design *design, RTLIL::Module *module)
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{
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if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
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return false;
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@ -266,9 +266,6 @@ struct FlattenWorker
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for (auto cell : module->selected_cells())
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{
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if (handled_cells.count(cell) > 0)
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continue;
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if (!design->has(cell->type))
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continue;
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@ -311,16 +308,13 @@ struct FlattenWorker
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for (auto cell : cells.sorted)
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{
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log_assert(handled_cells.count(cell) == 0);
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log_assert(cell == module->cell(cell->name));
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RTLIL::Module *tpl = design->module(cell->type);
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dict<IdString, RTLIL::Const> parameters(cell->parameters);
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if (tpl->get_blackbox_attribute(ignore_wb)) {
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handled_cells.insert(cell);
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if (tpl->get_blackbox_attribute(ignore_wb))
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continue;
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}
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std::pair<IdString, dict<IdString, RTLIL::Const>> key(cell->type, parameters);
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IdString derived_name;
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@ -401,18 +395,17 @@ struct FlattenPass : public Pass {
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if (mod->get_bool_attribute(ID::top))
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top_mod = mod;
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pool<RTLIL::Cell*> handled_cells;
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if (top_mod != nullptr) {
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worker.flatten_do_list.insert(top_mod->name);
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while (!worker.flatten_do_list.empty()) {
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auto mod = design->module(*worker.flatten_do_list.begin());
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while (worker.flatten_module(design, mod, handled_cells)) { }
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while (worker.flatten_module(design, mod)) { }
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worker.flatten_done_list.insert(mod->name);
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worker.flatten_do_list.erase(mod->name);
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}
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} else {
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for (auto mod : design->modules().to_vector())
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while (worker.flatten_module(design, mod, handled_cells)) { }
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while (worker.flatten_module(design, mod)) { }
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}
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log_suppressed();
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