be47e78289
[Arch] Change arch for Sapone test
2021-10-30 15:23:19 -07:00
e6cc3c4942
[Flow] Enable flatten for dff-related yosys scripts
2021-10-30 15:12:34 -07:00
ad5cce0ae8
[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
2021-10-30 15:11:07 -07:00
8dea7e80e6
[Flow] Update yosys script to not use sdff and dffe
2021-10-30 14:56:54 -07:00
40d11a45d9
[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
2021-10-30 14:49:56 -07:00
b7ad61227d
[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
2021-10-30 14:47:37 -07:00
ec184ef532
[Flow] Flatten the synthesis recipe in default yosys script to disable the mapping on DFFE and SDFF
2021-10-30 14:46:12 -07:00
0b770f3330
[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
2021-10-30 14:36:43 -07:00
59a622a910
[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
2021-10-30 14:34:37 -07:00
978c60e75b
[Flow] Disable DFFE and SDFF in no-ff Yosys scripts
2021-10-30 13:29:38 -07:00
18bab18032
[Test] Disable all the quicklogic tests due to missing support in Yosys v0.10 release
2021-10-30 13:20:58 -07:00
16de60e943
[Test] Turn off ACE2 run in bitstream generation only flows
2021-10-30 12:31:14 -07:00
94328351be
[Script] Replace deprecated ``rmdff`` in out-of-date yosys scripts
2021-10-30 12:00:06 -07:00
0a449cc24c
[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected
2021-10-30 11:45:01 -07:00
9c06041ce4
[Flow] Update yosys script by replacing the deprecated command 'opt_rmdff` with `opt_dff`
2021-10-30 11:27:40 -07:00
a355977420
Adding Yosys+Verific support.
2021-10-29 18:34:27 +05:00
b8d5920529
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
2021-10-28 15:45:58 -07:00
2eef21a1af
Fixed port names for mult_36x36
2021-10-26 19:14:43 +05:00
274252438a
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-10-20 20:13:46 +05:00
c42acec81e
Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py
2021-10-18 10:45:35 +00:00
c3dd704bf3
Fixing typo in run_fpga_flow.py
2021-10-18 09:13:42 +00:00
d411967159
Fixing small typo in run_fpga_flow.py
2021-10-15 10:01:12 +00:00
e0cfd46ec7
Merge remote-tracking branch 'upstream/master' into update_from_upstream
2021-10-14 19:25:31 +05:00
b2c4e3314e
[Test] Bug fix in test cases
2021-10-11 10:28:09 -07:00
8566e2a0cd
[Test] Renaming test case to follow naming convention as other fabric key test cases
2021-10-11 09:56:23 -07:00
2bf203cd00
[Test] Deploy the new test to basic regression test
2021-10-11 09:54:39 -07:00
b8b02d37d5
[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
2021-10-11 09:53:23 -07:00
cdcb07256b
[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization
2021-10-11 09:49:22 -07:00
982a324e0d
[Test] Temporarily disable some tests; Will go back later
2021-10-10 23:30:50 -07:00
40fd89fdb4
[arch] Update fabric key for multi-region
2021-10-10 22:03:49 -07:00
8f9e564cd5
[Test] Add the new test to basic regression test
2021-10-09 20:45:23 -07:00
6122863548
[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
2021-10-09 20:44:28 -07:00
82e77b42c5
[Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA
2021-10-09 20:43:55 -07:00
8aa2647878
[Script] Bug fix in slow clock frequency in shift register chain contraints
2021-10-06 16:49:01 -07:00
dc5aedc393
[Script] Correct naming for clocks in shifter register chain defined in simulation setting files
2021-10-06 13:36:35 -07:00
a1eaacf5a8
[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
2021-10-06 12:12:15 -07:00
554018449e
[Test] Update regression test script
2021-10-06 12:10:37 -07:00
b98a8ec718
[Test] Added the dedicated test case for fixed shift register clock frequency
2021-10-06 12:09:26 -07:00
169bb5fa45
[Script] Add an example simulation setting file with a fixed clock frequency for shift registers
2021-10-06 11:58:50 -07:00
189ade6c1e
[Test] Bug fix
2021-10-05 19:17:34 -07:00
f74ea5d39a
[Test] Use the new openfpga shell script in don't care bit tests
2021-10-05 19:14:44 -07:00
4add9781d5
[Script] Add a new openfpga shell script for don't care bits outputting
2021-10-05 19:13:50 -07:00
50604e4589
[Test] move test cases
2021-10-05 19:02:43 -07:00
064ac478f3
[Test] Deploy news test to fpga-bitstream regression tests
2021-10-05 19:01:03 -07:00
fed6c133b1
[Test] Add new tests to validate the correctness of bitstream files with don't care bits
2021-10-05 18:59:33 -07:00
80fd1efd61
[Test] Add an example test key for multi-region QuickLogic memory bank using shift registers
2021-10-05 11:46:58 -07:00
b21f212031
[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
2021-10-05 11:39:53 -07:00
492db50efe
[Test] Deploy the new test to basic regression tests
2021-10-05 10:59:26 -07:00
52569f808e
[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
2021-10-05 10:57:33 -07:00
d2859ca1c8
[Arch] Add an example architecture for multi-region QuickLogic memory bank using shift registers
2021-10-05 10:56:20 -07:00
fbef22b494
[Arch] Bug fix in the example architecture for QL memory bank using WLR and shift registers
2021-10-04 16:39:53 -07:00
13c31cb89c
[Test] Deploy the qlbanksr_wlr to basic regression tests
2021-10-04 16:37:49 -07:00
fa1908511d
[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
2021-10-04 16:36:20 -07:00
7f75c2b619
[Test] Deploy shift register -based QL memory bank test case to basic regression test
2021-10-03 16:06:44 -07:00
86e7c963f8
[Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files
2021-10-02 22:19:20 -07:00
0b06820177
[HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals
2021-10-01 17:06:35 -07:00
7ba5d27ea7
[Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model
2021-10-01 17:02:35 -07:00
ff6f7e80f6
[Flow] Modify simulation setting example for QuickLogic memory bank using separated clks for BL and WL shift registers
2021-10-01 16:52:06 -07:00
dda147e234
[Flow] Add an example simulation setting file for defining programming shift register clocks
2021-10-01 11:04:23 -07:00
7b010ba0f4
[Engine] Support programming shift register clock in XML syntax
2021-10-01 11:00:38 -07:00
fa57117f50
[Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers
2021-10-01 10:19:51 -07:00
41cc375746
[Arch] define default CCFF model in ql bank example architecture that uses shift registers
2021-09-29 16:34:40 -07:00
89a97d83bd
[Test] Added a new test case for the shift register banks in QuickLogic memory banks
2021-09-29 16:28:06 -07:00
4968f0d11f
Merge branch 'master' into qlbank_sr
2021-09-28 14:20:30 -07:00
80232fc459
[Arch] Add a new example architecture for QL memory bank using WLR in shift registers
2021-09-28 12:36:36 -07:00
4c04c0fbd7
[Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models
2021-09-28 12:35:42 -07:00
2ce2fb269a
[HDL] Added a different FF model which is designed to drive WLW only
2021-09-28 12:35:13 -07:00
6469ee3048
[HDL] Update DFF modules by adding custom cells required by shift registers in BL/WLs
2021-09-28 12:21:54 -07:00
4400dae108
[Test] Bug fix in the wrong arch name
2021-09-28 11:40:25 -07:00
4aed045cdd
[Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs
2021-09-28 11:34:20 -07:00
811c898173
[Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests
2021-09-28 11:29:45 -07:00
dae3554fd4
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
2021-09-28 11:27:49 -07:00
1ca1b0f3e9
[Test] Deploy the new test case (flatten BL/WL for QL memory bank) to basic regression tests
2021-09-22 15:58:05 -07:00
655b195d8b
[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
2021-09-22 15:56:44 -07:00
a98df811ed
[Arch] Bug fix: wrong circuit model name was used for CCFF
2021-09-22 15:50:47 -07:00
53da5d49fe
[Arch] Correct XML syntax errors
2021-09-22 15:48:14 -07:00
3cfd5c3531
[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
2021-09-22 15:04:59 -07:00
212c5bd642
[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
2021-09-22 15:04:19 -07:00
b0aaab9c03
[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
2021-09-22 11:32:13 -07:00
efed268585
[Test] Deploy new test (for multi-region QL memory bank) to basic regression tests
2021-09-22 11:30:08 -07:00
abfa380333
[Test] Added a test case to validate the fabric key of 2-region QL memory bank
2021-09-22 11:27:09 -07:00
337ed33b68
[Test] Added a sample fabric key for 2-region QL memory bank
2021-09-22 11:25:16 -07:00
7db7e2d8f6
[Test] Deploy the new test case for multi region QL memory bank to basic regression tests
2021-09-22 10:05:27 -07:00
d0fe12fadd
[Arch] Add an example OpenFPGA architecture for 2-region QL memory bank
2021-09-22 10:03:39 -07:00
51fc222d61
[Test] Added a new test case for multi-region QL memory bank
2021-09-22 10:01:33 -07:00
ab42239b94
[Test] Bug fix in the fabric key
2021-09-21 16:44:58 -07:00
f57aceff87
[Test] Deploy the load external key test case for ql memory bank to basic regression tests
2021-09-21 16:25:14 -07:00
aad47ffbc6
[Test] Upgrade the sample fabric key to ql memory bank for a 2x2 fabric
2021-09-21 16:22:50 -07:00
1412121541
[Test] Added a new test to validate the fabric key parser for QL memory bank
2021-09-21 16:20:24 -07:00
cd0d8b86fa
[Test] Add a random fabric key generated by OpenFPGA which is designed for QL memory bank
2021-09-21 15:55:34 -07:00
7327850cf3
[Test] Deploy the fabric key test case for ql memory bank to basic regression tests
2021-09-21 15:43:54 -07:00
dc2d1d1c3c
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
2021-09-21 15:42:20 -07:00
d36d1ebee2
[HDL] Temporarily disable WLR func in primitive HDL modeling
2021-09-20 17:07:51 -07:00
0450d57d82
[Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR
2021-09-20 16:05:01 -07:00
3f6ac41868
[Test] Deploy the WLR test to the basic regression tests
2021-09-20 11:21:58 -07:00
60fc3ab36c
[Test] Added a new test case for the WLR memory bank
2021-09-20 11:20:36 -07:00
5c1c428ea5
[HDL] Updated cell library with the SRAM cell with Read Enable signal
2021-09-20 11:13:36 -07:00
cd2978a434
[Arch] Added a new architecture example which shows how to use the memory bank with readback functionality
2021-09-20 11:13:02 -07:00
b867db815f
Update fpgaflow_default_tool_path.conf
...
Update regex for VPR
2021-09-17 14:02:26 +08:00
81a2ad58df
[Test] Deploy the ql memory bank test case to basic regression tests (run on CI)
2021-09-09 13:48:30 -07:00
b82cfdf555
[Test] Add the QL memory bank test to regression test cases
2021-09-09 09:29:21 -07:00
6be3c64f1c
[Arch] Add an example architecture using the physical design friendly memory bank organization
2021-09-09 09:22:27 -07:00
6adf439081
Merge remote-tracking branch 'upstream/master'
2021-09-01 14:19:00 -07:00
c31c1d8b04
Accept absolute project paths as inputs to the 'run_fpga_task.py' script.
2021-08-13 11:08:09 -04:00
9f03ecb160
[Test] Patch test case due to the changes in counter benchmarks
2021-07-02 17:57:39 -06:00
64dcdaec61
[Test] Update all the tasks that use counter benchmark
2021-07-02 17:29:13 -06:00
5a6874e9f1
[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks
2021-07-02 17:28:17 -06:00
8baf60603a
[Script] Patching the run_fpga_task.py on pin constraint files
2021-07-02 15:59:29 -06:00
fdf94cba83
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
2021-07-02 15:28:34 -06:00
3cbe266c44
[Test] Bug fix on the test case for multi-mode FF and pin constraints
2021-07-02 15:27:27 -06:00
c67807868c
[bugFix] Benchamrk variable declaration
2021-07-02 15:26:39 -06:00
3aacce2a96
Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
2021-07-02 14:04:42 -06:00
edd5be2cae
[CI] Added testcase for benchmark variable
2021-07-02 12:51:34 -06:00
dcb89cb16b
[Arch] Patch architecture due to missing mode bit definition
2021-07-02 11:41:29 -06:00
5286f9ba25
[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
2021-07-02 11:39:00 -06:00
02fd2a69b3
[Script] Add dff with active-low async reset to default yosys tech lib
2021-07-02 11:17:43 -06:00
477e535344
[HDL] Added a multi-mode FF design with configurable asynchronous reset
2021-07-02 11:13:03 -06:00
fd85f956c9
[Arch] Update k4n4 arch with true multi-mode flip-flop
2021-07-02 11:08:39 -06:00
0b6a9b06f5
[Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality
2021-07-02 10:39:07 -06:00
1de1f2f2e2
[FLOW] Variable in capital case
2021-07-01 22:26:00 -06:00
81f9dff9ff
[Flow] Allows benchmark specific var declaraton
2021-07-01 22:19:53 -06:00
1d281765ea
fixed tab spacing
2021-07-01 16:42:04 -06:00
808821bb8c
fixed errors
2021-07-01 16:40:03 -06:00
006b54c4bc
ready for merge
2021-07-01 15:35:39 -06:00
8513b8a4ff
Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
2021-07-01 15:29:39 -06:00
2567fbee05
ready to merge
2021-07-01 15:28:59 -06:00
04ceeefb0a
Merge branch 'master' into verilog_testbench
2021-07-01 14:43:26 -06:00
db9231c225
tests failing with initial blocks
2021-07-01 13:52:28 -06:00
be14e4f448
added design_variables.yml
2021-07-01 16:31:42 +05:00
6559f71082
added ci_scripts
2021-07-01 15:07:37 +05:00
fab2b069f0
added signal gen regression test to shell script
2021-06-30 16:18:09 -06:00
a898537474
[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``
2021-06-30 15:29:13 -06:00
83d177b13b
[Test] Deploy the newly added adder benchmarks to tests
2021-06-30 15:14:24 -06:00
4d4577bb83
[Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders
2021-06-30 15:13:47 -06:00
9eeec05a1f
[Test] Bug fix
2021-06-29 19:55:07 -06:00
f32ffb6d61
[Test] Bug fix
2021-06-29 18:51:28 -06:00
56b0428eba
[Misc] Bug fix
2021-06-29 18:48:19 -06:00
c6089385b0
[Misc] Bug fix
2021-06-29 18:34:41 -06:00
5f5a03f17f
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
2021-06-29 18:28:38 -06:00
2c1692e6dc
[Test] Bug fix
2021-06-29 17:54:25 -06:00
4fb34642ca
[Script] Add a new example script for global tile clock running full testbench
2021-06-29 17:53:56 -06:00
9655bc35cb
[Script] Bug fix due to the full testbench generation changes
2021-06-29 17:04:19 -06:00
cbea4a3cb6
[Test] Add the test cases to regression test
2021-06-29 16:08:22 -06:00
30c2f597f2
[Test] Added two cases to validate testbench generation without self checking
2021-06-29 16:06:15 -06:00
20faf82e64
[Script] Rename example script
2021-06-29 16:02:35 -06:00
01391fd81e
[Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features
2021-06-29 15:56:33 -06:00
7119075253
[Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated
2021-06-29 15:52:42 -06:00
75a12e55de
[HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes
2021-06-29 11:40:22 -06:00
b4c587f10b
[Test] Added the new test cases to regression tests
2021-06-27 19:58:15 -06:00
6f0600e17f
[Test] Added two test cases for generating preconfigured fabric wrapper in different styles
2021-06-27 19:56:01 -06:00
4a623bec79
[Script] Add example openfpga shell script to generate preconfigured fabric wrapper
2021-06-27 19:55:40 -06:00
fae5e1dfdf
[Script] Upgrade openfpga shell script with the new option '--embed_bitstream'
2021-06-25 15:16:37 -06:00
477cba1c7e
Merge branch 'master' into verilog_testbench
2021-06-23 09:18:18 -06:00
b2c30e3103
[Test] Bug fix in mcnc openfpga shell script
2021-06-22 16:40:24 -06:00
e34fbf8ecf
[Test] Deploy MCNC big20 to the micro benchmark regression test
2021-06-22 16:36:04 -06:00
f06017581c
[Test] Bug fix in counter micro benchmark tests
2021-06-22 16:33:50 -06:00
0a0d10b36d
[HDL] Bug fix in Verilog syntax
2021-06-22 16:18:46 -06:00
4421dfcbbd
Merge branch 'master' into micro_benchmark
2021-06-22 14:29:29 -06:00
fd580bb36f
[Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name
2021-06-22 11:45:23 -06:00
0b2d6eb147
[Test] Add micro benchmark to a dedicated regression test
2021-06-21 18:35:41 -06:00
760570d883
[Test] Update counter test case for cover most counter HDL design
2021-06-21 18:13:18 -06:00
9c24a739be
[Test] Added a MAC benchmark sweeping test
2021-06-21 17:40:53 -06:00
07dcf3ad27
[HDL] Add more micro benchmarks for counter, and-gate and mac unit
2021-06-21 16:48:35 -06:00
f9e66e1bae
[Script] Support benchmarks with same top module names in openfpga flow script; Now each benchmark local run directory has a unique name;
2021-06-21 15:27:12 -06:00
fce84e564d
[Script] Patch on missing string to show in error message
2021-06-18 11:20:35 -06:00
0e01177cf0
[Script] Now openfpga flow script output detailed error message when task is not found
2021-06-18 11:01:45 -06:00
96cb3081ab
Update fix_device_route_chan_width_example_script.openfpga
2021-06-18 09:51:16 -06:00
3cfc42cdf9
added testbench CI
2021-06-15 14:16:31 -06:00
d40cf98c48
[Test] Update test cases by using default net type in testbench generator
2021-06-14 11:47:28 -06:00
eed30605d7
[Test] patch test case
2021-06-09 15:20:55 -06:00
d545069aac
[Script] Bug fix
2021-06-09 14:50:37 -06:00
52c0ed571b
[Test] Patch test case to use proper template
2021-06-09 14:27:02 -06:00
c62666e7c3
[Test] Use proper template for some failing tests
2021-06-09 14:24:34 -06:00
4e3f589810
[Script] Patch openfpga shell script to use the new option '--support_icarus_simulator' for 'write_preconfigured_testbench'
2021-06-09 13:53:28 -06:00
f9404dc97d
[Script] Patch openfpga shell script due to missing a mandatory option in 'write_full_testbench'
2021-06-09 11:55:25 -06:00
9adf94bfd3
[Script] Update all the openshell scripts to deprecate 'write_verilog_testbench'
2021-06-09 11:18:52 -06:00
be26c06673
[Script] Update an example script to use 'write_preconfigured_fabric_wrapper' and 'write_preconfigured_testbench' in place of 'write_verilog_testbench'
2021-06-09 10:41:22 -06:00
462326aaa5
[Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench'
2021-06-07 21:50:00 -06:00
5ecd975ec7
[Test] Bug fix
2021-06-07 19:20:10 -06:00
9556f994b4
[Test] Use 'write_full_testbench' in all the memory bank -related test cases
2021-06-07 17:49:40 -06:00
a67196178e
[Test] Now use 'write_full_testbench' in configuration frame test cases
2021-06-07 13:58:15 -06:00
27fa15603a
[Tool] Patch test case due to changes in the template script
2021-06-04 18:17:47 -06:00
e9fa44cc25
[Tool] Add fast configuration to the write bitstream command in example shell script
2021-06-04 16:24:56 -06:00
5f96d440ec
[Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration
2021-06-04 11:48:05 -06:00
ec203d3a5c
[Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases
2021-06-04 11:35:23 -06:00
2068291de0
[Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases
2021-06-04 11:32:49 -06:00
aa4e1f5f9a
[Test] Update test case which uses write_full_testbench openfpga shell script
2021-06-04 11:29:43 -06:00
f5e90c9467
[Script] Update openfpga shell script with fast configuration option
2021-06-04 11:28:10 -06:00
ebe30fc070
[Test] Deploy write full testbench to multi-head configuration chain test case
2021-06-03 17:08:33 -06:00
8fc90637e0
[Script] Update write_full_testbench example script to support custom device layout in VPR
2021-06-03 17:08:08 -06:00
1e9f6eb439
[Test] update configuration chain test to use new testbench
2021-06-03 15:53:27 -06:00
51ca62a464
[Script] Add example script for write_full_testbench command
2021-06-03 15:48:59 -06:00
12b44e0eca
added configuration benchmark files
2021-05-13 10:04:23 -06:00
c33ca464dc
[Test] Deploy new tests to regression test
2021-05-07 12:06:46 -06:00
2baf3ddd2f
[Test] Add test cases for 'report_bitstream_distribution' command
2021-05-07 12:06:24 -06:00
7dc7c1b4f5
[Script] Add example openfpga shell script showing how to use 'report_bitstream_distribution' command
2021-05-07 12:05:47 -06:00
f1658cb735
[Test] Deploy blinking to test cases
2021-05-06 15:17:45 -06:00
16fff90607
[Benchmark] Add microbenchmark 1-bit blinking
2021-05-06 15:17:27 -06:00
f77b81fe5b
[Arch] recover the mem16k arch as it is used in other test cases
2021-04-28 15:05:30 -06:00
bc34efe337
[Arch] Bug fix in the architecture using BRAM spanning two columns
2021-04-28 14:32:17 -06:00
a5e40fbb21
Merge branch 'master' into micro_benchmarks
2021-04-28 14:27:58 -06:00
870432e7f1
[Test] Patch regression test script due to the change of DPRAM test case
2021-04-28 12:45:52 -06:00
b72d4bd807
[Test] Update test case for 1kbit DPRAM architectures
2021-04-28 11:28:53 -06:00
117cea295d
[Arch] Patch architecture to be compatible with pin names of DPRAM cell
2021-04-28 11:28:23 -06:00
a571b063b6
[Benchmark] Add 1k DPRAM benchmark which can fit new arch
2021-04-28 11:26:31 -06:00
c24edbd674
[Script] Update yosys script due to arch changes in DPRAM sizes
2021-04-28 10:55:59 -06:00
ec4b60f3cc
[Arch] Add example arch using 1-kbit DPRAM
2021-04-28 10:47:17 -06:00
be98775ae5
[Arch] Reduce the size of DPRAM in example architecture to accelerate testing
2021-04-28 10:45:10 -06:00
5c729657ef
[Test] Bug fix in test case for DPRAM whose width = 2
2021-04-28 10:31:22 -06:00
79b27a6329
[Arch] Patch arch using DPRAM block with wide = 2
2021-04-28 10:29:09 -06:00
63309ba72b
[HDL] Patch dpram cell
2021-04-27 23:42:31 -06:00
411af10933
[Script] Patch yosys script for 16kbit dual port RAM
2021-04-27 23:41:47 -06:00
834657f2da
[Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes
2021-04-27 23:41:14 -06:00
0bec4b3f32
[Test] Update task configuration to use proper openfpgashell script
2021-04-27 23:34:42 -06:00
7d059f7407
[Benchmark] Bug fix in dual port ram 16k benchmark
2021-04-27 23:33:20 -06:00
3c1c33bf1e
[Benchmark] Add a microbenchmark just fit 16k dual port ram
2021-04-27 22:51:43 -06:00
7e2368158e
[Benchmark] move benchmarks to microbenchmark category
2021-04-27 22:12:30 -06:00
5a85ec9fa0
[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised
2021-04-27 22:09:10 -06:00
dd46780865
[Script] Update yosys script using BRAMs
2021-04-27 21:44:27 -06:00
fdfbdc4613
[Test] Update task configuration files to use dedicated yosys script
2021-04-27 20:05:04 -06:00
2802b0895c
[HDL] Add yosys technology library for reworked architecture using 16k-bit DPRAM
2021-04-27 19:55:46 -06:00
e67095edd2
[HDL] Add 16k-bit dual port ram verilog
2021-04-27 19:55:16 -06:00
0f8aaae2bc
[Arch] Patch architecture using 16kbit dual port RAM
2021-04-27 19:54:34 -06:00
1d498bb296
[Benchmark] Add a scalable micro benchmark fifo
2021-04-27 15:26:52 -06:00
6cb4d7d720
[Test] Add the new test to regressiont test
2021-04-27 14:41:38 -06:00
b8ced5377f
[Test] Add a test case for i/o mapping writer
2021-04-27 14:41:15 -06:00
f9fd444b86
[Script] Add an write I/O mapping example script for openfpga shell
2021-04-27 14:40:26 -06:00
1d5e926d9e
[Test] Deploy new test to CI
2021-04-26 16:29:54 -06:00
6291871faf
[Test] Added a test for the example architecture with 2x2 DSP blocks
2021-04-26 16:28:43 -06:00
8c007c7c49
[Arch] Add a new example architecture where a DSP block occupies a 2x2 grid
2021-04-26 16:28:10 -06:00
7d4c5e3cd1
[Arch] Patch pin location of dsp8 to be evenly placed on the right side of a height=2 block
2021-04-26 12:00:57 -06:00
6e87b8875b
[Arch] Patch the pin location of frac dsp16 to appear on the top side of a height=2 block
2021-04-26 11:59:25 -06:00
b7da22501c
[Test] Deply new test to regression test
2021-04-24 15:55:05 -06:00
5adffad602
[Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!!
2021-04-24 15:49:53 -06:00
80f98328df
[Test] Update test settings for architecture with fracturable DSP blocks
2021-04-24 15:16:50 -06:00
8b8096f3a8
[HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block
2021-04-24 14:57:09 -06:00
a3a98fa21d
[Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition
2021-04-24 14:56:10 -06:00
4f454abfde
[Arch] Add a new architecture using fracturable 16-bit DSP blocks
2021-04-24 14:01:42 -06:00
272d1fffb7
[HDL] Add tech library for architecture using multi-mode 16-bit DSP blocks
2021-04-24 13:30:46 -06:00
ddcdb35b28
[Arch] Bug fix in single-mode 8-bit DSP architectures
2021-04-24 13:30:03 -06:00
1c6b9a23d7
[Test] Add new test for multi-mode 16-bit DSP blocks
2021-04-24 13:29:29 -06:00
c44688739d
[HDL] Add verilog netlist for the fracturable 16-bit multiplier blocks
2021-04-23 22:12:26 -06:00
09cc7f0007
[Script] Enable constant net routing for heterogeneous FPGAs
2021-04-23 20:44:36 -06:00
189c94ff19
[Test] Deploy new mac benchmarks to tests
2021-04-23 20:44:14 -06:00
200b6d39a6
[Benchmark] Add more micro benchmarks for mac ranging from 8 bit to 32 bit
2021-04-23 20:36:28 -06:00
671394ec2c
[Benchmark] Add microbenchmarks for mac with different sizes for DSP testing
2021-04-23 20:33:43 -06:00
cbb7d41b6e
[Script] Enable constant net routing for VTR benchmarks
2021-04-23 14:15:13 -06:00
784713e88a
[Test] Add golden results for IWLS2005 as a simple QoR check
2021-04-22 19:27:31 -06:00
a16896054d
[Script] Enable constant net routing for iwls benchmarks
2021-04-22 19:16:32 -06:00
1dcb8e39a9
[Test] Unlock more IWLS'2005 benchmarks in testing
2021-04-22 09:23:33 -06:00
61a473e479
[Test] Unlock more IWLS'2005 benchmarks under testing thanks to flexible FF mapping support
2021-04-21 22:56:19 -06:00
5a519390ff
[HDL] Enriched DFF model in yosys technology library
2021-04-21 22:49:05 -06:00
ce6018e123
[Arch] Enriched DFF model to support active-low/high FFs
2021-04-21 22:48:31 -06:00
adfea88be2
[HDL] Rename multi-mode DFF module
2021-04-21 20:06:03 -06:00
62497549b6
[HDL] Add multi-mode DFF module
2021-04-21 20:04:40 -06:00
3a5c26c6a1
[Test] Update IWLS test by using new architecture and customize DFF techmap
2021-04-21 19:51:25 -06:00
8cbea6a268
[HDL] Add technology library for customizable DFF synthesis
2021-04-21 19:50:51 -06:00
3d615e1516
[Script] Add yosys script supporting customize DFF/BRAM/DSP mapping
2021-04-21 19:50:07 -06:00
9d9840d9b7
[Arch] Add architecture using multi-mode DFFs
2021-04-21 19:49:48 -06:00
8046b16c15
[Test] Remove restrictions in the multi-clock test case and deploy new microbenchmarks for testing
2021-04-21 14:04:34 -06:00
b203ef7bc2
[Benchmark] Add new benchmark 2-clock version of and2_latch as an essential test for multi-clock FPGAs
2021-04-21 14:03:51 -06:00
2fa370d7d5
[Test] Patch regression tests for fpga bitstream
2021-04-19 17:15:14 -06:00
64163edbe6
[Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting
2021-04-19 16:15:25 -06:00
578d81b67a
[Test] Patch task configuration file
2021-04-19 16:15:00 -06:00
18eb5c9de9
[Test] Deploy new test to CI
2021-04-19 15:56:41 -06:00
5976cc0a1c
[Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection
2021-04-19 15:54:18 -06:00
7018073e28
[Script] Update openfpga shell script w/o ace usage to adapt pin constraint files
2021-04-17 15:04:51 -06:00
da95da933b
[Test] Add pin constraint file to map reset to correct FPGA pins
2021-04-17 15:04:26 -06:00
e3dafe99da
[Arch] Revert to old version arch due to editing by mistake
2021-04-16 20:58:32 -06:00
c020333512
Merge branch 'master' into dff_techmap
2021-04-16 20:54:28 -06:00
7172fc9ea1
[Test] Patch test for architecture using asynchronous DFFs
2021-04-16 20:48:37 -06:00
0a15f366cb
[HDL] Patch dff models used in yosys tech map
2021-04-16 20:48:15 -06:00
16e02ef485
[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
2021-04-16 20:47:39 -06:00
1c2f91b7e6
[Script] Patch yosys script with dff tech map
2021-04-16 20:47:18 -06:00
2666726f36
[Script] Remove clock routing from example openfpga shell script without ace
2021-04-16 20:46:49 -06:00
23d08757cf
[Script] Add example script without using ACE2
2021-04-16 20:20:10 -06:00
bbdc0e53af
[Benchmark] Add 8-bit counter benchmark using asynchronous reset to test fracff architectures
2021-04-16 20:14:48 -06:00
b11d03f9c5
[Test] Deploy new test to CI
2021-04-16 20:01:40 -06:00
93be81abe1
[Test] Add test case for architecture using DFF with reset
2021-04-16 20:00:48 -06:00
5414a6a3da
[Script] Add yosys script with custom DFF tech mapping
2021-04-16 20:00:30 -06:00
4239bb4e68
[Arch] Patch architecture files using multi-mode DFFs
2021-04-16 19:59:55 -06:00
f2f7f010ea
[Arch] Add new architectures using DFF with reset in VPR
2021-04-16 19:26:18 -06:00
64294ae4eb
[Doc] Update README for architecture files due to new architecture features
2021-04-16 19:25:54 -06:00
ff4460695b
[HDL] Add dff tech map files for yosys
2021-04-16 17:00:55 -06:00
e46c6e75a3
[Benchmark] Add missing RTL for IWLS2005 benchmarks
2021-04-16 16:50:41 -06:00
87587bbb74
[Test] Add iwls2005 benchmarks to regression tests
2021-04-16 16:12:05 -06:00
1566a5558a
[Test] Add task configuration file for iwls2005
2021-04-16 16:10:31 -06:00
43bf016576
[Script] Add example openfpga shell script for iwls benchmark
2021-04-16 16:09:47 -06:00
26d3b5a954
[Benchmark] Reorganize iwls2005 benchmark: separate the location of rtl and testbenches
2021-04-16 16:08:58 -06:00
86ad572530
[Benchmark] Add opencore RTLs from IWLS 2005 benchmarks
2021-04-16 14:27:54 -06:00
b469705819
Merge branch 'master' into fpga_sdc_test
2021-04-11 21:14:46 -06:00
1db8bd7eec
[Test] Update regression test with new SDC tests
2021-04-11 20:24:32 -06:00
07f6066c11
[Script] Update timing unit in SDC example script
2021-04-11 20:24:18 -06:00
94c4c817eb
[Test] Expand sdc time unit test to sweep all the available units
2021-04-11 20:14:09 -06:00
a4893e27cf
[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
2021-04-11 17:26:27 -06:00
44d97ead86
Merge branch 'master' into hetergeneous_arch
2021-03-23 17:05:03 -06:00
b00b4f0f5f
[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian
2021-03-23 15:44:53 -06:00
d82ffe0cbf
[Test] Deploy MAC_8 benchmark to regression test
2021-03-23 15:36:28 -06:00
108c84a022
[HDL] Add HDL for 8-bit single-mode multiplier
2021-03-23 15:36:09 -06:00
145a80de43
[Script] Add an openfpga shell script for heterogeneous fpga verification
2021-03-23 15:35:34 -06:00
fdec72b5bc
[Arch] Add an example architecture with 8-bit single-mode multiplier
2021-03-23 15:35:06 -06:00
be03eafd66
[Benchmark] Add a micro benchmark: 8-bit multiply and accumulate
2021-03-23 15:33:37 -06:00
8c970a792a
[Test] Add a new test case for heterogeneous FPGA using single-mode 8-bit multiplier
2021-03-23 15:33:00 -06:00
6b0409da60
[Script] Add a template yosys script support only DSP mapping
2021-03-23 15:32:10 -06:00
a4bbffd1aa
[HDL] Add yosys tech lib for a DSP-only heterogeneous FPGA
2021-03-23 15:30:41 -06:00
fff16a01ab
[Test] Update tolerance when checking VTR benchmark QoR
2021-03-23 12:27:20 -06:00
781880ed93
[Script] Add tolerance options to check qor script
2021-03-23 12:26:33 -06:00
e3f8a6cf7a
[Test] Deploy QoR check to VTR benchmark regression test
2021-03-23 11:15:22 -06:00
351dec5935
[Test] Add QoR csv file for vtr benchmarks
2021-03-23 11:15:02 -06:00
23e7f7f1f5
[Script] Update default list of result extraction for openfpga flow
2021-03-23 11:06:42 -06:00
adfbd28a7a
[Script] Add a simple QoR checker
2021-03-23 11:06:16 -06:00
61eddb08de
[Test] Update task configuration by commenting out high-runtime VTR benchmarks
2021-03-22 14:42:42 -06:00
55d1004cf2
[Benchmark] Add missing DPRAM module to LU32PEEng
2021-03-22 14:41:38 -06:00
5fc83ebea3
[Benchmark] Add missing DPRAM modules to LU8PEEng
2021-03-22 14:38:00 -06:00
b828f91a78
[Benchmark] Add missing DPRAM and SPRAM modules to mcml
2021-03-22 14:13:05 -06:00
d050f1b746
[Script] Enable fast bitstream generation for VTR benchmarks
2021-03-22 12:54:36 -06:00
4bfd0c0a02
[Test] Enable more VTR benchmark in testing
2021-03-22 12:53:30 -06:00
b906ab814e
[Benchmark] Add missing DPRAM module to mkPktMerge
2021-03-22 12:51:23 -06:00
310c2a9495
[Benchmark] Add missing DPRAM module to mkDelayWorker32B
2021-03-22 12:51:02 -06:00
707247283c
[Benchmark] Add missing DPRAM module to mkSMAdapter4B
2021-03-22 12:50:39 -06:00
eb056e2afd
[Benchmark] Add missing DPRAM module to or1200
2021-03-22 12:50:17 -06:00
7fd345a616
[Script] Solved the problem on BRAM mapping in the yosys script supporting both DSP and BRAMs
2021-03-22 10:39:47 -06:00
cc10b10703
[Test] Enable more benchmarks for testing; See problems when mapping BRAMs
2021-03-20 22:53:37 -06:00
169ee53b79
[Benchmark] Add missing modules to VTR benchmarks
2021-03-20 22:53:17 -06:00
eca2a35612
[Script] Add route chan width option to vtr openfpga script
2021-03-20 22:00:09 -06:00
9a3aff274f
[Test] Use fix routing channel width to save runtime for VTR benchmarks
2021-03-20 21:59:44 -06:00
ca9a70fc88
[Test] Comment out benchmarks have problems in synthesis
2021-03-20 21:29:21 -06:00
125e94a6b3
[Test] Add full VTR benchmark (with most commented); ready for massive testing
2021-03-20 21:01:18 -06:00
2bd8ef2af9
[Benchmark] Patch boundtop.v with missing SPRAM module
2021-03-20 21:00:53 -06:00
cb07848475
[Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation
2021-03-20 18:11:54 -06:00
f3792bc6f6
[Test] Update VTR benchmark test case to include DSP example benchmark
2021-03-20 18:09:19 -06:00
477a522885
[HDL] Rename tech lib to be consistent with arch name changes
2021-03-20 18:08:03 -06:00
911979a731
[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
2021-03-20 18:04:59 -06:00
1185f7b8bf
[Script] Add a template yosys script to enable DSP mapping
2021-03-20 17:05:30 -06:00
6bf4880c50
[benchmark] Add vtr benchmark
2021-03-17 15:24:26 -06:00
f9dc7c1b54
[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells
2021-03-17 15:15:22 -06:00
08a86e056a
[Test] Add vtr benchmark regression test
2021-03-17 15:13:58 -06:00
7eeb35d21f
[Script] Bug fix in yosys script to synthesis BRAM
2021-03-17 15:12:04 -06:00
1976a8068f
[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
2021-03-17 15:11:17 -06:00
deee7ba366
[Script] Add example script to run vtr benchmarks
2021-03-17 15:10:56 -06:00
910f8471dd
[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
2021-03-17 15:10:05 -06:00
76113a80fa
[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture
2021-03-17 15:09:12 -06:00
e1f8b252b1
Merge branch 'master' into yosys_heterogeneous_block_support
2021-03-16 20:05:21 -06:00
d12a8a03fd
[Test] Update test case using yosys bram parameters
2021-03-16 19:52:17 -06:00
094b3e9b90
[Script] Use parameters in template yosys script supporting BRAMs
2021-03-16 19:51:48 -06:00
cea43c2c45
[HDL] Add SPRAM module to generic yosys tech lib for openfpga usage
2021-03-16 18:04:31 -06:00
73b06256d0
[Test] Deploy the new yosys script supporting BRAM to regression tests
2021-03-16 16:52:59 -06:00
84778bd38d
[Script] Add new yosys script to support architectures with BRAMs
2021-03-16 16:52:18 -06:00
090f483a11
[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
2021-03-16 16:45:57 -06:00
76837e02e6
[Script] Rename yosys script supporting bram and restructure techlib files
2021-03-16 16:16:53 -06:00
e61857aa2b
Merge branch 'master' into ganesh_dev
2021-03-11 19:17:02 -07:00
366bec232c
[Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI
2021-03-11 15:25:48 -07:00
bb2a02c9ad
[HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[ https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v ]
2021-03-11 15:23:14 -07:00
baf162e401
[Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification
2021-03-10 22:45:19 -07:00
a6186db315
[Test] Update bitstream annotation with new syntax
2021-03-10 20:45:17 -07:00
7d07f5d8cb
[Test] Update bitstream setting example with mode bit overwriting
2021-03-10 15:34:53 -07:00
b42541d84e
[Flow] Support multiple iterations in rewriting yosys scripts
2021-03-10 14:10:35 -07:00
90a00da1df
[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'
2021-03-10 13:56:35 -07:00
d21909ad6c
[Test] Use custom rewriting script in lut_adder test
2021-03-10 13:48:20 -07:00
0e772bc3b4
[Script] Patch the yosys rewrite script to avoid existing blif outputs
2021-03-10 13:47:30 -07:00
7adb78b159
[Script] Add a template yosys script with rewriting at the end
2021-03-10 13:40:31 -07:00
035043d0d8
[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
2021-03-10 13:36:11 -07:00
5d46537b5b
[Script] Allow users to specify custom post-synthesis verilog for simulation
2021-03-10 11:45:55 -07:00
aafd87c3f9
[Flow] Update flow-run to support custom yosys rewrite scripts
2021-03-10 11:36:29 -07:00
db8ea86b2f
update tests to use no_ff_map and remove tests that need async set/reset for now
2021-03-10 10:04:45 -08:00
608bd1f658
comment out desings that utilize local async reset/preset
2021-03-09 19:24:01 -08:00
7f4c20ff33
comment out desings that utilize local async reset/preset
2021-03-09 10:37:06 -08:00
c4b83aeaa9
bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type
2021-03-09 00:46:40 -08:00
2daa770319
[Arch] Update openfpga architecture to include quicklogic cell sim
2021-03-08 21:40:29 -07:00
812d8c950e
[Script] Update quicklogic's script to output correct verilog file name
2021-03-08 21:39:44 -07:00
37aa42d305
[Test] Patch task configuration file for lut_adder_test to use correct rewrite script
2021-03-08 21:38:51 -07:00
c53c41b7a5
[Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file
2021-03-08 21:09:23 -07:00
131643dcc0
[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
2021-03-08 21:08:55 -07:00
b860722893
Fixed parameter ys_rewrite_params name bug
2021-03-08 10:34:39 -07:00
52de55e7eb
Merge branch 'master' into ganesh_dev
2021-03-08 10:15:06 -07:00
906d2fa72d
Merge branch 'master' into shift_reg
2021-03-08 09:24:29 -07:00
7a35811430
[Flow] Yosys rewrite support
2021-03-08 00:35:47 -07:00
67cd9a69b7
[Flow] Extended yosys variable subtitution
2021-03-08 00:21:07 -07:00
7945628307
Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification
2021-03-07 22:25:01 -08:00
6a1ce01084
Replacing YOSYS_FAMILY & YOSYS_MODE with YOSYS_ARGS
2021-03-07 22:02:11 -08:00
ce76c58422
add shift register test case
2021-03-05 09:06:05 -08:00
2b2acae757
Adding command to generate verilog file out of yosys run
2021-03-05 04:07:02 -08:00
0cbad747a1
Incorporating review comments on approach to follow to dynamically select yosys_mode and yosys_family
2021-03-04 01:10:47 -08:00
817729ac86
Added variable YOSYS_MODE, YOSYS_FAMILY in ys script to dynamically pick adder/no_adder mode or family. User can specify their choice in SYNTHESIS_PARAM: bench_yosys_mode, bench_yosys_family variables
2021-03-01 22:31:15 -08:00
e34380a654
Merge branch 'master' into default_net_type
2021-03-01 08:38:58 -07:00
ea4aee8cb2
For time-being yosys script running in no_adder mode.
2021-02-28 22:07:23 -08:00
0038496d9c
Replacing -openfpga with -family qlf_k4n8
2021-02-28 21:08:47 -08:00
b4b6ada06f
[Script] Correct bugs in example scripts using default_net_type
2021-02-28 16:31:44 -07:00
86930d63d3
[Test] Deploy new test to CI
2021-02-28 16:18:46 -07:00
b90a17543d
[Test] Add new test case to test default nettype in different verilog syntax
2021-02-28 16:16:45 -07:00
9f4d05da67
[Test] Bug fix for new test case
2021-02-28 16:11:30 -07:00
8cc2c7d924
[Script] Bug fix for default net type example script
2021-02-28 12:35:44 -07:00
6d419fed41
[Test] Deploy verilog default net wire type test case to CI
2021-02-28 12:33:48 -07:00
18a7041424
[Test] Add default net type test for explicit port mapping
2021-02-28 12:31:32 -07:00
0723b79bce
[Script] Add example script for verilog default net type
2021-02-28 12:29:56 -07:00
27200e3daa
[Test] Update regression test cases for fpga verilog
2021-02-28 12:24:36 -07:00
ff29cc3dff
[Test] Move tests to a test group
2021-02-28 12:23:35 -07:00
9cb1ca42fe
[Test] Deploy default net type option to test case
2021-02-28 12:20:43 -07:00
ae05871b1f
[Script] Remove default net type from an example script; Limit it to some test cases
2021-02-28 12:19:14 -07:00
d7eb159726
[Script] Add default net type option to example openfpga shell scripts
2021-02-28 12:08:30 -07:00
0d82e4939c
[Test] Use unified quicklogic synthesis script and enable end-of-flow tests
2021-02-26 09:35:40 -07:00
744d87cb4e
[Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues
2021-02-26 09:34:52 -07:00
870d3a0e27
Merge branch 'master' into dev
2021-02-26 09:28:42 -07:00
1082d3c677
Renaming file qlf_k4n8_yosys.ys to qlf_yosys.ys
2021-02-25 23:39:07 -08:00
1e48d4f6dc
Modifying custom yosys script file name
2021-02-25 22:21:39 -08:00
4c2a88e27f
[Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed
2021-02-24 11:51:10 -07:00
0ce9b66c75
[Arch] Add a dummy adder lut circuit model to support HDL simulation
2021-02-24 10:09:44 -07:00
86a602d381
[Test] Deploy new test to CI
2021-02-23 19:55:07 -07:00
a62786986b
[Test] Turn off verification in adder lut test temporarily
2021-02-23 19:03:25 -07:00
ad25944e59
[Arch] Patched superLUT architecture example when trying adder8 synthesis script
2021-02-23 19:00:27 -07:00
53df7f69e7
[Test] Bug fix in the test case using lut adder
2021-02-23 16:59:46 -07:00
db71cc8a16
[Test] Add LUT adder test using quicklogic synthesis script
2021-02-23 16:50:58 -07:00
19f6b221b1
[Test] Rework comments on runtime
2021-02-22 15:25:57 -07:00
4803b0ce42
[Test] Add test case for sdc controller
2021-02-22 15:02:14 -07:00
c7a9a4e896
[Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs
2021-02-22 15:01:50 -07:00
ca135f3325
[Arch] Add flagship architecture with 8-clock
2021-02-22 15:01:18 -07:00
2e2b1cb6e7
[Test] Use hetergenenous FPGA architecture in quicklogic tests
2021-02-22 13:41:04 -07:00
1c09c55e9f
[Arch] Add hetergenenous 8-clock FPGA architecture
2021-02-22 13:38:50 -07:00
b3fed683f9
[Test] Deploy test to CI
2021-02-22 12:43:30 -07:00
bc30f62c5a
[Test] Add test for sdc controller
2021-02-22 12:41:53 -07:00
60dc194d8f
[Test] Bug fix in the 5clock test case
2021-02-22 11:46:23 -07:00
71e0026a50
[Test] Add new test for 5-clock counter to quicklogic tests
2021-02-22 11:32:17 -07:00
2bb588dacf
[Flow] Add a new script for generating bitstream for multi-clock architectures
2021-02-22 11:31:24 -07:00
77896379e2
[Arch] Add simulation setting for 8-clock architectures
2021-02-22 11:10:03 -07:00
16debe49f6
[Arch] Add more comments on the 4 clock simulation setting file
2021-02-22 11:04:34 -07:00
0ac75723af
[Arch] Add new architecture with 8 clocks
2021-02-22 11:00:45 -07:00
b9c2564a7e
[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
2021-02-22 10:49:21 -07:00
bc8aa0ebc6
[Test] Remove routing test from quicklogic's flow test
2021-02-22 10:22:47 -07:00
2dbdc2644f
[Benchmark] Remove replicate micro benchmarks
2021-02-22 10:22:19 -07:00
9b6b2068ee
[Test] Move MCNC test to benchmark sweep test group
2021-02-22 10:18:34 -07:00
c1f4a434e4
[Doc] Update README for the regression test tasks
2021-02-22 10:17:02 -07:00
d6a02a985e
Merge pull request #248 from lnis-uofu/add_quicklogic_tests
...
Disabling verilog testbench generation for quicklogic tests
2021-02-22 09:02:29 -07:00
d842026672
Disabling verilog testbench generation for quicklogic tests
2021-02-21 21:58:23 -08:00
be5e0cdea9
Merge pull request #241 from lnis-uofu/add_quicklogic_tests
...
Adding quicklogic tests and updating the corresponding conf file to r…
2021-02-22 09:50:26 +05:30
576e6753f6
Removing 2 more tests which are variant of and design
2021-02-19 09:11:19 -08:00
d4c5a5655a
Removing blif file as well as and2 testcase
2021-02-19 08:55:17 -08:00
6de0954ca5
Uncommenting all benchmarks except 2 that requires multiple clocks
2021-02-19 08:40:26 -08:00
e08ac1a41e
[Test] Deploy synthesizable verilog test to CI
2021-02-18 19:37:45 -07:00
e19fc15fec
[Test] bug fix in test case
2021-02-18 19:37:45 -07:00
affc8cbbc4
[Test] Deploy test to CI
2021-02-18 19:37:45 -07:00
2e88b035ed
[Test] Add wire LUT repacker test case
2021-02-18 19:37:44 -07:00
1f097abe99
[Benchmark] Add micro benchmark for FIR filter
2021-02-18 19:37:44 -07:00
69cdc11ea5
Uncommenting the tests that are running fine
2021-02-18 04:17:12 -08:00
d85d6e964e
Merge pull request #227 from watcag/master
...
Standard-cell flow
2021-02-17 10:11:34 -07:00
7ee01711c2
Merge remote-tracking branch 'origin/master' into add_quicklogic_tests
2021-02-17 00:06:59 -08:00
44a979288b
Adding quicklogic tests and updating the corresponding conf file to run them
2021-02-16 23:08:38 -08:00
a819375f69
[Script] Bug fix on the run_fpga_flow.py script when power analysis is disabled
2021-02-16 16:53:13 -07:00
2c2e493739
[Test] Remove quicklogic test from basic tests
2021-02-16 12:29:10 -07:00
9c19e2b365
[Test] Move regression test scripts from workflow to openfpga_flow
2021-02-16 11:55:47 -07:00
426b6449d8
change the test to turn off power analysis
2021-02-15 02:45:38 -08:00
3a587f663a
copy yosys output file in case power analysis setting is off
2021-02-15 02:36:02 -08:00
e683e00032
[HDL] Add disclaimer for the frac_lut4_arith HDL codes
2021-02-10 14:50:11 -07:00
9b86f3bb85
Merge branch 'master' into dev
2021-02-09 22:40:45 -07:00
22e675148e
[HDL] Add HDL codes for a super LUT with embedded carry logic
2021-02-09 21:13:22 -07:00
b81b74aa7c
[Arch] Patch architecture to support superLUT-related XML syntax
2021-02-09 20:23:32 -07:00
7dcc14d73f
[Arch] Bug fix in the example arch with super LUT
2021-02-09 15:52:22 -07:00
3ae501a5ea
[Test] Update test case to use dedicated eblif file
2021-02-09 15:51:57 -07:00
1712ee4edb
[Benchmark] Add a dedicated eblif to test the frac lut4 arith architecture
2021-02-09 15:41:21 -07:00
4c7f4bd82f
ahoy nice
2021-02-09 17:38:19 -05:00
2b51b36dd6
[Test] Now use the super LUT arch in the test case
2021-02-09 15:27:44 -07:00
56284059de
[Test] Add a test case for a super LUT
2021-02-09 15:25:32 -07:00
304b26c97f
[Arch] Add example architectures for superLUT circuit model
2021-02-09 15:11:12 -07:00
71c76df063
default to ns for time unit -- synopsys dc whines
2021-02-09 17:08:38 -05:00
6bb2e29f17
default to ns for time unit -- synopsys dc whines
2021-02-09 17:04:52 -05:00
87c69460df
what is going on
2021-02-09 11:33:08 -05:00
cc74c6268a
trying fix chan width
2021-02-09 11:28:19 -05:00
95fe4d7dae
adding dff synth
2021-02-09 10:34:54 -05:00
b14b5f975d
adding sweep for W
2021-02-09 08:48:25 -05:00
d7967da328
bugfix in alt
2021-02-08 23:04:00 -05:00
485708423c
no need for dff*, but need tap_buf4
2021-02-08 23:00:13 -05:00
cf154d8bb9
no need for dff*, but need tap_buf4
2021-02-08 22:29:55 -05:00
e14c0bf0c4
no need for dff*, but need tap_buf4
2021-02-08 22:28:42 -05:00
45437fbc46
no need for dff*, but need tap_buf4
2021-02-08 22:27:57 -05:00
853bf8af43
typos fixed;
2021-02-08 22:03:14 -05:00
d040ba569c
merge for consideration;
2021-02-08 21:29:34 -05:00
94f858fcde
merge for consideration;
2021-02-08 21:27:01 -05:00
0c6d27cf7e
merge for consideration;
2021-02-08 21:26:48 -05:00
b4185f7e8c
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA
2021-02-08 21:11:30 -05:00
2344cdcabc
merge
2021-02-08 21:11:28 -05:00
1ce94040da
Merge pull request #221 from lnis-uofu/flow_dev
...
[Flow] Support multi-user environment for running task
2021-02-08 12:43:57 -07:00
80a4872ba0
Merge pull request #222 from lnis-uofu/gg_cleanup
...
[Flow] ACE is optional during flow script, only runs when power estimation is on
2021-02-08 10:08:47 -07:00
ede5f8ed58
[Flow] Support multi-user enviroment for running task
2021-02-07 22:11:04 -07:00
00fc3d7622
Merge pull request #217 from lnis-uofu/dev
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Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
2021-02-05 09:53:28 -07:00
ee14c15e58
Merge pull request #212 from lnis-uofu/soft_adder_lut_support
...
Support overloading LUT bitstream from attributes in .eblif file format
2021-02-04 21:55:02 -07:00
8853370c60
[Script, Benchmark, Test] Now use circuit format in openfpga shell script to specify eblif file
2021-02-04 20:20:10 -07:00
dc09c47411
[Arch] Remove packable from architecture files and replace with disable_packing
2021-02-04 18:03:56 -07:00
224bf6c686
Merge branch 'master' into dev
2021-02-04 17:21:15 -07:00
66bc370c4d
[Arch] Use disable_packing in architecture library
2021-02-04 16:29:03 -07:00
a4c266d59a
[Arch] Add pack patterns for soft adders; Still fail in packing
2021-02-03 19:11:15 -07:00
6cdc31f073
[Flow] ACE is optional duign flow script
2021-02-03 19:07:48 -07:00
cac1160bf7
[Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution
2021-02-03 11:20:56 -07:00
df4a397470
[Cleanup] Removed deadcode
2021-02-03 10:35:14 -07:00
4c825b27b3
[Benchmark] Change to use adder lut4 to be consistent with architecture
2021-02-03 09:37:48 -07:00
31441c0b64
[Test] Deploy adder_8 to soft adder test
2021-02-03 09:26:38 -07:00
05d63567d0
[Benchmark] Use latest adder eblif file
2021-02-03 09:21:38 -07:00
ebe66dea35
Bumping up latest yosys changes related to adder tech mapping
2021-02-03 14:30:06 +05:30
2c06960e4f
[Benchmark] Add subckt definition to micro benchmark and2.eblif
2021-02-02 15:51:16 -07:00
021520783b
[Arch] Add dummy timing info to adder_lut4 and carry_follower model
2021-02-02 15:49:43 -07:00
dc320182b0
[Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models
2021-02-02 15:04:43 -07:00
8e36ed1ab6
[Test] Update task configuration to use and2 eblif
2021-02-02 15:01:15 -07:00
62803dc044
[Benchmark] Add eblif example for and2 benchmark
2021-02-02 14:59:31 -07:00
5e2847bc41
[Test] Update test case to use eblif file
2021-02-02 09:33:41 -07:00
39e6f62d91
[Benchmark] Use eblif in naming the adder_8 micro benchmark
2021-02-02 09:32:42 -07:00
d3397f6936
[Script] Remove activity from bitstream setting example script
2021-02-02 09:25:36 -07:00
9ff5e7926b
[Test] Update test case to use the adder benchmark
2021-02-02 09:24:39 -07:00
7f14dfbe87
[Script] Add example script to use bitstream setting
2021-02-02 09:18:08 -07:00
04594cb7ab
[Test] Adapt bitstream annotatin file to parser's requirement
2021-02-01 17:38:36 -07:00
280c9620aa
[Test] Add an example bitstream annotation file
2021-02-01 16:01:21 -07:00
a6354fab7c
[Arch] Decide to move external bitstream definition to a separated XML file
2021-02-01 15:57:44 -07:00
df88e2adc0
[Arch] Add an example definition of external bitstream to openfpga arch with soft adder
2021-02-01 14:26:11 -07:00
10302752a7
[Arch] Bug fix in architecture. Now soft adder modes are accepted
2021-02-01 13:43:39 -07:00
d8927e12e8
[Arch] Add soft adder operating mode to test architecture
2021-02-01 12:25:37 -07:00
7f0f7a1c70
[Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script
2021-02-01 12:05:04 -07:00
b215b868c1
[HDL] Bug fix in HDL netlist due to port name mismatching
2021-02-01 11:35:25 -07:00
e4abe263c3
[Arch] Bug fix
2021-02-01 11:29:27 -07:00
fb05e1a938
[Arch] bug fix due to using openfpga cell library
2021-02-01 11:27:21 -07:00
940dce469a
[Test] Bug fix for test case configuration
2021-02-01 11:19:47 -07:00
a80acfb547
[Test] Add new test case to CI script
2021-02-01 11:16:12 -07:00
af630dab1e
[Test] Add soft adder test case. This is placeholder. Test arch will be elaborated
2021-02-01 10:53:38 -07:00
9cce411eda
[Test] Add adder test cases
2021-02-01 10:42:24 -07:00
0eb949b85a
[Arch] Now use the MUX2 cell from openfpga cell library for the QLSOFA
2021-02-01 10:34:32 -07:00
e0e2506e32
[HDL] Remove redundant comments
2021-02-01 10:33:08 -07:00
39543f7945
[HDL] Add carry mux2 to cell library
2021-02-01 10:23:46 -07:00
6ede799c16
[Arch] Add openfpga architecture for the QLSOFA
2021-02-01 10:15:35 -07:00
df05911d24
Merge branch 'master' into soft_adder_lut_support
2021-02-01 10:02:05 -07:00
9bbf214456
[Arch] Update the caravel architecture
2021-01-29 17:00:17 -07:00
a70725b4be
Merge branch 'master' into dev
2021-01-29 11:41:40 -07:00
8b74947737
[Script] Now multi-clock openfpga shell script no longer needs activity file
2021-01-29 11:40:33 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
0b82b6439b
[Regression] Upgraded runtime enviroment to python3.8
2021-01-26 16:40:45 -07:00
af0646260c
[Test] Bug fix in pin constraints
2021-01-19 17:44:05 -07:00
186f2f1968
[Test] Use pin constraint in multi-clock test case
2021-01-19 17:42:40 -07:00
3fdd5ae8b3
[Script] Use pin constraints in template script
2021-01-19 17:42:25 -07:00
e17a5cbbf2
[Test] Rename to pin constraint to comply with libpcf requirement
2021-01-19 15:52:51 -07:00
ab25e1af5f
[Test] Add example XML for net mapping between benchmark to FPGA
2021-01-19 09:29:21 -07:00
ea9d6bfe91
[Flow] Update the design constraint file to follow bug fix in parser
2021-01-17 10:41:01 -07:00
dd74f05a31
[Test] Add repack constraints to tests
2021-01-17 10:35:36 -07:00
12e0efd03e
[Script] Add an example openfpga script to use repack design constraints
2021-01-17 10:33:56 -07:00
d0e05b3575
[Lib] Now use pb_type in design constraints instead of physical tiles
2021-01-16 21:35:43 -07:00
8578c1ecac
[Flow] Rename the design contraint file syntax
2021-01-16 15:35:13 -07:00
9154cfdeec
[Flow] Add comments for the design constraint file
2021-01-16 15:34:01 -07:00
6ab0f71896
[Test] Add an example of repack pin constraints file
2021-01-16 14:38:39 -07:00
89f9d24d32
[Flow] Update simulation settings for multiple clock to allow unique clock port name
2021-01-15 10:35:43 -07:00
dbed04b53b
[Flow] Reduce the number of clock cycles to simulation in example sim setting XML for a light test run in CI
2021-01-14 15:42:21 -07:00
3b5394b45f
[Test] Now use dedicated simulation settings for the 4-clock architecture
2021-01-14 15:40:16 -07:00
923f3a3401
[Flow] Add an example simulation settings for a 4-clock FPGA fabric
2021-01-13 17:29:39 -07:00
9a906e787b
[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock
2021-01-13 15:43:31 -07:00
314e458632
[Test] Update task configuration to use post-yosys .v file in verification
2021-01-13 15:42:45 -07:00
c5a2027f36
[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
2021-01-13 15:41:48 -07:00
7af6d7f07d
[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation
2021-01-13 15:38:44 -07:00
tangxifan
Aram Kostanyan
nadeemyaseen-rs
Christophe Alexandre
slt
Will
Ganesh Gore
ANDREW HARRIS POND
komaljaved-rs
Andrew Pond
Tarachand Pagarani
Lalit Sharma
Lalit Narain Sharma
Nachiket Kapre
AurelienAlacchi