riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests

This commit is contained in:
tangxifan 2021-09-28 11:29:45 -07:00
parent dae3554fd4
commit 811c898173
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
openfpga_flow/regression_test_scripts/basic_reg_test.sh
View File

@ -58,6 +58,7 @@ run-task basic_tests/full_testbench/ql_memory_bank --debug --show_thread_logs
run-task basic_tests/full_testbench/ql_memory_bank_use_wlr --debug --show_thread_logs
run-task basic_tests/full_testbench/multi_region_ql_memory_bank --debug --show_thread_logs
run-task basic_tests/full_testbench/ql_memory_bank_flatten --debug --show_thread_logs
run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr --debug --show_thread_logs
echo -e "Testing testbenches without self checking features";
run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs