From 811c898173f0e8a72b01351077fba7b948473f73 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 28 Sep 2021 11:29:45 -0700 Subject: [PATCH] [Test] Add the QL mem flatten BL/WL with WLR test to basic regression tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index cc74b9a4a..b9067ce78 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -58,6 +58,7 @@ run-task basic_tests/full_testbench/ql_memory_bank --debug --show_thread_logs run-task basic_tests/full_testbench/ql_memory_bank_use_wlr --debug --show_thread_logs run-task basic_tests/full_testbench/multi_region_ql_memory_bank --debug --show_thread_logs run-task basic_tests/full_testbench/ql_memory_bank_flatten --debug --show_thread_logs +run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr --debug --show_thread_logs echo -e "Testing testbenches without self checking features"; run-task basic_tests/full_testbench/full_testbench_without_self_checking --debug --show_thread_logs