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[Test] Deploy MAC_8 benchmark to regression test

This commit is contained in:
tangxifan 2021-03-23 15:36:28 -06:00
parent 108c84a022
commit d82ffe0cbf
1 changed files with 3 additions and 0 deletions
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openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
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@ -44,6 +44,9 @@ run-task fpga_verilog/bram/dpram16k --debug --show_thread_logs
echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
run-task fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
echo -e "Testing Verilog generation with heterogeneous fabric using 8-bit single-mode multipliers ";
run-task fpga_verilog/dsp/single_mode_mult_8x8 --debug --show_thread_logs
echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
run-task fpga_verilog/io/multi_io_capacity --debug --show_thread_logs