[HDL] Add HDL for 8-bit single-mode multiplier

openfpga_flow/openfpga_cell_library/verilog/mult_8x8.v

@@ -0,0 +1,16 @@
+//-----------------------------------------------------
+// Design Name : mult_8x8
+// File Name   : mult_8x8.v
+// Function    : A 8-bit multiplier
+// Coder       : Xifan Tang
+//-----------------------------------------------------
+
+module mult_8x8 (
+  input [0:7] A,
+  input [0:7] B,
+  output [0:15] Y
+);
+
+  assign Y = A * B;
+
+endmodule