From 108c84a022babebc649fc2d4d4c49b740d4074f3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 23 Mar 2021 15:36:09 -0600
Subject: [PATCH] [HDL] Add HDL for 8-bit single-mode multiplier

---
 .../openfpga_cell_library/verilog/mult_8x8.v     | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 openfpga_flow/openfpga_cell_library/verilog/mult_8x8.v

diff --git a/openfpga_flow/openfpga_cell_library/verilog/mult_8x8.v b/openfpga_flow/openfpga_cell_library/verilog/mult_8x8.v
new file mode 100644
index 000000000..a8649488b
--- /dev/null
+++ b/openfpga_flow/openfpga_cell_library/verilog/mult_8x8.v
@@ -0,0 +1,16 @@
+//-----------------------------------------------------
+// Design Name : mult_8x8
+// File Name   : mult_8x8.v
+// Function    : A 8-bit multiplier
+// Coder       : Xifan Tang
+//-----------------------------------------------------
+
+module mult_8x8 (
+  input [0:7] A,
+  input [0:7] B,
+  output [0:15] Y
+);
+
+  assign Y = A * B;
+
+endmodule