[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised

openfpga_flow/benchmarks/micro_benchmark/fifo/rtl/fifo.v

@@ -2,8 +2,8 @@
 // Reference: 
 //   https://embeddedthoughts.com/2016/07/13/fifo-buffer-using-block-ram-on-a-xilinx-spartan-3-fpga/
 module fifo
-  #( parameter ADDRESS_WIDTH = 12, // number of words in ram
-                 DATA_WIDTH    =  8  // number of bits in word
+  #( parameter ADDRESS_WIDTH = 4, // number of words in ram
+                 DATA_WIDTH    =  4  // number of bits in word
    )
    
   // IO ports
@@ -94,4 +94,4 @@ module fifo
    // assign full/empty status to output ports
    assign full  = full_reg;
    assign empty = empty_reg;
-endmodule
+endmodule

openfpga_flow/benchmarks/micro_benchmark/fifo/rtl/sync_dual_port_ram.v

@@ -2,8 +2,8 @@
 // Reference: 
 //   https://embeddedthoughts.com/2016/07/13/fifo-buffer-using-block-ram-on-a-xilinx-spartan-3-fpga/
 module sync_dual_port_ram
-		#( parameter ADDRESS_WIDTH = 12, // number of words in ram
-                     DATA_WIDTH    =  8  // number of bits in word
+		#( parameter ADDRESS_WIDTH = 4, // number of words in ram
+                     DATA_WIDTH    =  4  // number of bits in word
 	 )
 	
 	// IO ports
@@ -32,4 +32,4 @@ module sync_dual_port_ram
 	// assignments for two data out ports
 	assign read_data_out  = ram[read_address_reg];
 	assign write_data_out = ram[write_address_reg];
-endmodule
+endmodule