[HDL] Patch the yosys techlib for the heterogeneous FPGA by using little endian

openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v

@@ -1,9 +1,9 @@
 module $__MY_DPRAM_1024x8 (
-  output [7:0] B1DATA,
+  output [0:7] B1DATA,
   input CLK1,
-  input [9:0] B1ADDR,
-  input [9:0] A1ADDR,
-  input [7:0] A1DATA,
+  input [0:9] B1ADDR,
+  input [0:9] A1ADDR,
+  input [0:7] A1DATA,
   input A1EN,
   input B1EN );
 

openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_cell_sim.v

@@ -5,15 +5,15 @@
 module dpram_1024x8_core (
   input wclk,
   input wen,
-  input [9:0] waddr,
-  input [7:0] data_in,
+  input [0:9] waddr,
+  input [0:7] data_in,
   input rclk,
   input ren,
-  input [9:0] raddr,
-  output [7:0] data_out );
+  input [0:9] raddr,
+  output [0:7] data_out );
 
-  reg [7:0] ram[1023:0];
-  reg [7:0] internal;
+  reg [0:7] ram[0:1023];
+  reg [0:7] internal;
 
   assign data_out = internal;
 
@@ -40,10 +40,10 @@ module dpram_1024x8 (
   input clk,
   input wen,
   input ren,
-  input [9:0] waddr,
-  input [9:0] raddr,
-  input [7:0] data_in,
-  output [7:0] data_out );
+  input [0:9] waddr,
+  input [0:9] raddr,
+  input [0:7] data_in,
+  output [0:7] data_out );
 
     dpram_1024x8_core memory_0 (
       .wclk    (clk),
@@ -61,9 +61,9 @@ endmodule
 // 36-bit multiplier
 //-----------------------------
 module mult_36(
-  input [35:0] A,
-  input [35:0] B,
-  output [71:0] Y
+  input [0:35] A,
+  input [0:35] B,
+  output [0:71] Y
 );
 
 assign Y = A * B;

openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v

@@ -1,7 +1,7 @@
 module mult_36x36 (
-  input [35:0] A,
-  input [35:0] B,
-  output [71:0] Y
+  input [0:35] A,
+  input [0:35] B,
+  output [0:71] Y
 );
   parameter A_SIGNED = 0;
   parameter B_SIGNED = 0;