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[Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model

This commit is contained in:
tangxifan 2021-10-01 17:02:35 -07:00
parent ff6f7e80f6
commit 7ba5d27ea7
2 changed files with 6 additions and 4 deletions
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5
openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
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@ -173,7 +173,7 @@
<port type="input" prefix="D" lib_name="SIN" size="1"/>
<port type="output" prefix="Q" lib_name="SOUT" size="1"/>
<port type="bl" prefix="BL" lib_name="BL" size="1"/>
<port type="clock" prefix="sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register_clock="true"/>
<port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register_clock="true"/>
</circuit_model>
<!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
<circuit_model type="ccff" name="WL_DFFRQ" prefix="WL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
@ -184,7 +184,8 @@
<port type="input" prefix="D" lib_name="SIN" size="1"/>
<port type="output" prefix="Q" lib_name="SOUT" size="1"/>
<port type="wl" prefix="wl" lib_name="WLW" size="1"/>
<port type="clock" prefix="sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register_clock="true"/>
<port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register_clock="true"/>
</circuit_model>
</circuit_library>
<configuration_protocol>

5
openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_wlr_openfpga.xml
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@ -174,7 +174,7 @@
<port type="input" prefix="D" lib_name="SIN" size="1"/>
<port type="output" prefix="Q" lib_name="SOUT" size="1"/>
<port type="bl" prefix="BL" lib_name="BL" size="1"/>
<port type="clock" prefix="sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
<port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
</circuit_model>
<!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
<circuit_model type="ccff" name="WLR_DFFRQ" prefix="WLR_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
@ -186,7 +186,8 @@
<port type="output" prefix="Q" lib_name="SOUT" size="1"/>
<port type="wl" prefix="wl" lib_name="WLW" size="1"/>
<port type="wlr" prefix="wlr" lib_name="WLR" size="1"/>
<port type="clock" prefix="sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
<port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
</circuit_model>
</circuit_library>
<configuration_protocol>