From 7ba5d27ea7cb260ac383ca57ae72f727d68cbdda Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 1 Oct 2021 17:02:35 -0700
Subject: [PATCH] [Arch] Reworked example architectures for QuickLogic memory
 bank using shift registers: Add write-enable signal to WL CCFF model

---
 openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml | 5 +++--
 .../openfpga_arch/k4_N4_40nm_qlbanksr_wlr_openfpga.xml       | 5 +++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
index ce848d2e7..a21c0e522 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
@@ -173,7 +173,7 @@
        <port type="input" prefix="D" lib_name="SIN" size="1"/>
        <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
        <port type="bl" prefix="BL" lib_name="BL" size="1"/>
-       <port type="clock" prefix="sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register_clock="true"/>
+       <port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register_clock="true"/>
     </circuit_model>
     <!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
     <circuit_model type="ccff" name="WL_DFFRQ" prefix="WL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
@@ -184,7 +184,8 @@
        <port type="input" prefix="D" lib_name="SIN" size="1"/>
        <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
        <port type="wl" prefix="wl" lib_name="WLW" size="1"/>
-       <port type="clock" prefix="sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register_clock="true"/>
+       <port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register_clock="true"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_wlr_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_wlr_openfpga.xml
index 43d716222..da0e46ded 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_wlr_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_wlr_openfpga.xml
@@ -174,7 +174,7 @@
        <port type="input" prefix="D" lib_name="SIN" size="1"/>
        <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
        <port type="bl" prefix="BL" lib_name="BL" size="1"/>
-       <port type="clock" prefix="sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
+       <port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
     </circuit_model>
     <!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
     <circuit_model type="ccff" name="WLR_DFFRQ" prefix="WLR_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
@@ -186,7 +186,8 @@
        <port type="output" prefix="Q" lib_name="SOUT" size="1"/>
        <port type="wl" prefix="wl" lib_name="WLW" size="1"/>
        <port type="wlr" prefix="wlr" lib_name="WLR" size="1"/>
-       <port type="clock" prefix="sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
+       <port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>