[Test] Deploy MCNC big20 to the micro benchmark regression test
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@ -136,9 +136,3 @@ run-task fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
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echo -e "Testing through channels in tileable routing";
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run-task fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
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run-task fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
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# Verify MCNC big20 benchmark suite with ModelSim
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# Please make sure you have ModelSim installed in the environment
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# Otherwise, it will fail
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#run-task fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
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#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
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@ -7,6 +7,11 @@ PYTHON_EXEC=python3.8
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# OpenFPGA Shell with VPR8
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##############################################
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echo -e "Micro benchmark regression tests";
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# TODO: enable this when flow-run script support same top module name in one task configuration file
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#run-task benchmark_sweep/counter --debug --show_thread_logs
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run-task benchmark_sweep/counter --debug --show_thread_logs
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run-task benchmark_sweep/mac_units --debug --show_thread_logs
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# Verify MCNC big20 benchmark suite with ModelSim
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# Please make sure you have ModelSim installed in the environment
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# Otherwise, it will fail
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run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
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#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
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