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Update fpgaflow_default_tool_path.conf 

Update regex for VPR
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slt 2021-09-17 14:02:26 +08:00 committed by GitHub
parent 30feb78469
commit b867db815f
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1 changed files with 2 additions and 2 deletions
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openfpga_flow/misc/fpgaflow_default_tool_path.conf
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@ -24,8 +24,8 @@ mult_blocks = "Netlist mult_36 blocks: ([0-9]+)", str
memory_blocks = "Netlist memory blocks: ([0-9]+)", str
logic_delay = "Total logic delay: ([0-9.]+)", str
total_net_delay = "total net delay: ([0-9.]+)", str
total_routing_area = "Total routing area: ([0-9.]+)", str
total_logic_block_area = "Total used logic block area: ([0-9]+)", str
total_routing_area = "Total routing area: ([0-9.]+[e|E\+[0-9]+)", str
total_logic_block_area = "Total used logic block area: ([0-9.]+[e|E\+[0-9]+)", str
total_wire_length = "Total wirelength: ([0-9]+)", str
packing_time = "Packing took ([0-9.]+) seconds", str
placement_time = "Placement took ([0-9.]+) seconds", str