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tests failing with initial blocks

This commit is contained in:
ANDREW HARRIS POND 2021-07-01 13:52:28 -06:00
parent fab2b069f0
commit db9231c225
5 changed files with 29 additions and 33 deletions
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8
openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
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@ -29,10 +29,10 @@ module clock_divider (
reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter;
initial begin
clkdiv_counter <= 0;
clk_out <= 0;
end
// initial begin
// clkdiv_counter <= 0;
// clk_out <= 0;
// end
// Divide pl_clk (50MHz) to 1MHz
always @(posedge clk_in) begin

14
openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
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@ -36,13 +36,13 @@ module pulse_generator(
reg pulse_start;
reg pulse_end;
initial begin
pulse <= INITIAL_VALUE;
pulse_start <= 1'b0;
pulse_end <= 1'b0;
wait_cycle_counter <= 0;
pulse_width_counter <= 0;
end
// initial begin
// pulse <= INITIAL_VALUE;
// pulse_start <= 1'b0;
// pulse_end <= 1'b0;
// wait_cycle_counter <= 0;
// pulse_width_counter <= 0;
// end
// Wait a number of clock cycles, hold the initial value
always @(posedge clk_in) begin

11
openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh
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@ -1,11 +0,0 @@
#!/bin/bash
set -e
source openfpga.sh
PYTHON_EXEC=python3.8
###############################################
# OpenFPGA Shell with VPR8
##############################################
echo -e "Benchmark sweep tests";
run-task benchmark_sweep/signal_gen --debug --show_thread_logs

7
openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh
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@ -7,14 +7,15 @@ PYTHON_EXEC=python3.8
# OpenFPGA Shell with VPR8
##############################################
echo -e "Micro benchmark regression tests";
run-task benchmark_sweep/counter --debug --show_thread_logs
run-task benchmark_sweep/mac_units --debug --show_thread_logs
# run-task benchmark_sweep/counter --debug --show_thread_logs
# run-task benchmark_sweep/mac_units --debug --show_thread_logs
# Verify MCNC big20 benchmark suite with ModelSim
# Please make sure you have ModelSim installed in the environment
# Otherwise, it will fail
run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
# run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
run-task benchmark_sweep/signal_gen --debug --show_thread_logs

22
openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf
View File

@ -16,23 +16,29 @@ timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=
openfpga_fast_configuration=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
[SYNTHESIS_PARAM]
bench0_top = pulse_generator
# bench1_top = reset_generator
# bench2_top = clock_divider
bench0_top = clock_divider
bench0_chan_width = 300
bench1_top = pulse_generator
bench1_chan_width = 300
# bench2_top = reset_generator
# bench2_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=