From db9231c2251a6be9e20f0c75181b596d54a6a783 Mon Sep 17 00:00:00 2001 From: ANDREW HARRIS POND Date: Thu, 1 Jul 2021 13:52:28 -0600 Subject: [PATCH] tests failing with initial blocks --- .../signal_gen/clock_divider.v | 8 +++---- .../signal_gen/pulse_generator.v | 14 ++++++------ .../benchmark_sweep_test.sh | 11 ---------- .../micro_benchmark_reg_test.sh | 7 +++--- .../signal_gen/config/task.conf | 22 ++++++++++++------- 5 files changed, 29 insertions(+), 33 deletions(-) delete mode 100755 openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v index 4127cd9f3..8172b7c6d 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v @@ -29,10 +29,10 @@ module clock_divider ( reg [CLK_DIVIDER_SIZE - 1:0] clkdiv_counter; - initial begin - clkdiv_counter <= 0; - clk_out <= 0; - end + // initial begin + // clkdiv_counter <= 0; + // clk_out <= 0; + // end // Divide pl_clk (50MHz) to 1MHz always @(posedge clk_in) begin diff --git a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v index a73fc37f6..ff3391d55 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +++ b/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v @@ -36,13 +36,13 @@ module pulse_generator( reg pulse_start; reg pulse_end; - initial begin - pulse <= INITIAL_VALUE; - pulse_start <= 1'b0; - pulse_end <= 1'b0; - wait_cycle_counter <= 0; - pulse_width_counter <= 0; - end + // initial begin + // pulse <= INITIAL_VALUE; + // pulse_start <= 1'b0; + // pulse_end <= 1'b0; + // wait_cycle_counter <= 0; + // pulse_width_counter <= 0; + // end // Wait a number of clock cycles, hold the initial value always @(posedge clk_in) begin diff --git a/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh b/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh deleted file mode 100755 index 01f278fe9..000000000 --- a/openfpga_flow/regression_test_scripts/benchmark_sweep_test.sh +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/bash - -set -e -source openfpga.sh -PYTHON_EXEC=python3.8 -############################################### -# OpenFPGA Shell with VPR8 -############################################## - -echo -e "Benchmark sweep tests"; -run-task benchmark_sweep/signal_gen --debug --show_thread_logs \ No newline at end of file diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 0790421bb..44ecacd30 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -7,14 +7,15 @@ PYTHON_EXEC=python3.8 # OpenFPGA Shell with VPR8 ############################################## echo -e "Micro benchmark regression tests"; -run-task benchmark_sweep/counter --debug --show_thread_logs -run-task benchmark_sweep/mac_units --debug --show_thread_logs +# run-task benchmark_sweep/counter --debug --show_thread_logs +# run-task benchmark_sweep/mac_units --debug --show_thread_logs # Verify MCNC big20 benchmark suite with ModelSim # Please make sure you have ModelSim installed in the environment # Otherwise, it will fail -run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs +# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim +# run-task basic_tests/full_testbench/configuration_chain --debug --show_thread_logs run-task benchmark_sweep/signal_gen --debug --show_thread_logs diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index b1f3d4e47..6158af998 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -16,23 +16,29 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/configuration_chain_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v -# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v -# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v [SYNTHESIS_PARAM] -bench0_top = pulse_generator -# bench1_top = reset_generator -# bench2_top = clock_divider +bench0_top = clock_divider +bench0_chan_width = 300 + +bench1_top = pulse_generator +bench1_chan_width = 300 + +# bench2_top = reset_generator +# bench2_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= -#vpr_fpga_verilog_formal_verification_top_netlist=