[HDL] Added a different FF model which is designed to drive WLW only

This commit is contained in:
tangxifan 2021-09-28 12:35:13 -07:00
parent 6469ee3048
commit 2ce2fb269a
1 changed files with 28 additions and 0 deletions

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@ -472,6 +472,34 @@ endmodule //End Of Module
// @note This DFF is designed to drive WLs when shift registers are used
//-----------------------------------------------------
module WL_DFFRQ (
input RST, // Reset input
input CK, // Clock Input
input SIN, // Data Input
output SOUT, // Q output
output WLW // Drive WL write signals
);
//------------Internal Variables--------
reg q_reg;
//-------------Code Starts Here---------
always @ ( posedge CK or posedge RST)
if (RST) begin
q_reg <= 1'b0;
end else begin
q_reg <= SIN;
end
assign SOUT = q_reg;
assign WLW = q_reg;
endmodule //End Of Module
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active high reset
// @note This DFF is designed to drive WLs and WLRs when shift registers are used
//-----------------------------------------------------
module WLR_DFFRQ (
input RST, // Reset input
input CK, // Clock Input
input SIN, // Data Input