[HDL] Added a different FF model which is designed to drive WLW only

openfpga_flow/openfpga_cell_library/verilog/dff.v

@@ -472,6 +472,34 @@ endmodule //End Of Module
 // @note This DFF is designed to drive WLs when shift registers are used
 //-----------------------------------------------------
 module WL_DFFRQ (
+  input RST, // Reset input
+  input CK, // Clock Input
+  input SIN, // Data Input
+  output SOUT, // Q output
+  output WLW // Drive WL write signals
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST)
+if (RST) begin
+  q_reg <= 1'b0;
+end else begin
+  q_reg <= SIN;
+end
+
+assign SOUT = q_reg;
+assign WLW = q_reg;
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+// @note This DFF is designed to drive WLs and WLRs when shift registers are used
+//-----------------------------------------------------
+module WLR_DFFRQ (
   input RST, // Reset input
   input CK, // Clock Input
   input SIN, // Data Input