[HDL] Add more micro benchmarks for counter, and-gate and mac unit

openfpga_flow/benchmarks/micro_benchmark/and4/and4.v

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+/////////////////////////////////////////
+//  Functionality: 4-input AND 
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module and4(
+  a,
+  b,
+  c,
+  d,
+  e);
+
+input wire a;
+input wire b;
+input wire c;
+input wire d;
+output wire e;
+
+assign e = a & b & c & d;
+
+endmodule

openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v

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+///////////////////////////////////////////
+//  Functionality: Counter with asynchronous reset
+//  Author:        Xifan Tang
+////////////////////////////////////////
+
+module counter (
+	clk,
+	reset,
+	result
+);
+
+	input clk;
+	input reset;
+	output [127:0] result;
+
+	reg [127:0] result;
+
+	always @(posedge clk or posedge reset)
+	begin
+		if (reset) 
+			result = 0;		
+		else 
+			result = result + 1;
+	end
+endmodule		

openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter_tb.v

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+module counter_tb;
+
+  reg clk, reset;
+  wire [127:0] result;
+
+  counter DUT(
+    .clk(clk), 
+    .reset(reset), 
+    .result(result)
+  );
+  
+  initial begin
+    #0 reset = 1'b1; clk = 1'b0;
+    #100 reset = 1'b0;
+  end
+
+  always begin
+    #10 clk = ~clk;
+  end
+  
+  initial begin
+    #5000 $stop;
+  end
+
+endmodule

openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v

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+///////////////////////////////////////////
+//  Functionality: Counter with asynchronous reset
+//  Author:        Xifan Tang
+////////////////////////////////////////
+
+module counter (
+	clk,
+	resetb,
+	result
+);
+
+	input clk;
+	input reset;
+	output [127:0] result;
+
+	reg [127:0] result;
+
+	always @(posedge clk or negedge resetb)
+	begin
+		if (~resetb) 
+			result = 0;		
+		else 
+			result = result + 1;
+	end
+endmodule		

openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter_tb.v

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+module counter_tb;
+
+  reg clk, resetb;
+  wire [127:0] result;
+
+  counter DUT(
+    .clk(clk), 
+    .resetb(resetb), 
+    .result(result)
+  );
+  
+  initial begin
+    #0 reset = 1'b0; clk = 1'b0;
+    #100 reset = 1'b1;
+  end
+
+  always begin
+    #10 clk = ~clk;
+  end
+  
+  initial begin
+    #5000 $stop;
+  end
+
+endmodule

openfpga_flow/benchmarks/micro_benchmark/mac/mac_18/mac_18.v

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+//-------------------------------------------------------
+//  Functionality: A 18-bit multiply-acculumate circuit
+//  Author:        Xifan Tang
+//-------------------------------------------------------
+
+module mac_18(a, b, c, out);
+parameter DATA_WIDTH = 18;  /* declare a parameter. default required */
+input [DATA_WIDTH - 1 : 0] a, b, c;
+output [DATA_WIDTH - 1 : 0] out;
+
+assign out = a * b + c;
+
+endmodule
+
+
+
+
+
+
+
+
+

openfpga_flow/benchmarks/micro_benchmark/mac/mac_20/mac_20.v

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+//-------------------------------------------------------
+//  Functionality: A 20-bit multiply-acculumate circuit
+//  Author:        Xifan Tang
+//-------------------------------------------------------
+
+module mac_20(a, b, c, out);
+parameter DATA_WIDTH = 20;  /* declare a parameter. default required */
+input [DATA_WIDTH - 1 : 0] a, b, c;
+output [DATA_WIDTH - 1 : 0] out;
+
+assign out = a * b + c;
+
+endmodule
+
+
+
+
+
+
+
+
+

openfpga_flow/benchmarks/micro_benchmark/mac/mac_36/mac_36.v

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+//-------------------------------------------------------
+//  Functionality: A 36-bit multiply-acculumate circuit
+//  Author:        Xifan Tang
+//-------------------------------------------------------
+
+module mac_36(a, b, c, out);
+parameter DATA_WIDTH = 4;  /* declare a parameter. default required */
+input [DATA_WIDTH - 1 : 0] a, b, c;
+output [DATA_WIDTH - 1 : 0] out;
+
+assign out = a * b + c;
+
+endmodule
+
+
+
+
+
+
+
+
+

openfpga_flow/benchmarks/micro_benchmark/mac/mac_8_9/mac_8_9.v

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+//-------------------------------------------------------
+//  Functionality: 
+//    - A 8-bit multiply-acculumate circuit 
+//    - A 9-bit multiply-acculumate circuit
+//  Author:        Xifan Tang
+//-------------------------------------------------------
+
+module mac_8_9(a, b, c, out);
+parameter DATA_WIDTH = 18;  /* declare a parameter. default required */
+input [DATA_WIDTH - 1 : 0] a, b, c;
+output [DATA_WIDTH - 1 : 0] out;
+
+assign out[8:0] = a[8:0] * b[8:0] + c[8:0];
+assign out[17:9] = a[17:9] * b[17:9] + c[17:9];
+
+endmodule
+
+
+
+
+
+
+
+
+

openfpga_flow/benchmarks/micro_benchmark/mac/mac_9/mac_9.v

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+//-------------------------------------------------------
+//  Functionality: A 9-bit multiply-acculumate circuit
+//  Author:        Xifan Tang
+//-------------------------------------------------------
+
+module mac_9(a, b, c, out);
+parameter DATA_WIDTH = 9;  /* declare a parameter. default required */
+input [DATA_WIDTH - 1 : 0] a, b, c;
+output [DATA_WIDTH - 1 : 0] out;
+
+assign out = a * b + c;
+
+endmodule
+
+
+
+
+
+
+
+
+