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[Misc] Bug fix

This commit is contained in:
tangxifan 2021-06-29 18:48:19 -06:00
parent c6089385b0
commit 56b0428eba
1 changed files with 0 additions and 2 deletions
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openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga
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@ -58,8 +58,6 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --bitstream fabric_bitstream.bit
write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC
write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH}
# Write the SDC files for PnR backend
# - Turn on every options here