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[Test] Use fix routing channel width to save runtime for VTR benchmarks

This commit is contained in:
tangxifan 2021-03-20 21:59:44 -06:00
parent ca9a70fc88
commit 9a3aff274f
1 changed files with 3 additions and 0 deletions
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3
openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf
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@ -25,6 +25,9 @@ yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/
yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_bram_map.v
yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm_dsp_map.v
yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36
# VPR parameters
# Use a fixed routing channel width to save runtime
vpr_route_chan_width=300
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_40nm.xml