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[Flow] Add an example simulation setting file for defining programming shift register clocks

This commit is contained in:
tangxifan 2021-10-01 11:04:23 -07:00
parent 7b010ba0f4
commit dda147e234
1 changed files with 2 additions and 1 deletions
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3
openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_shift_register/config/task.conf
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@ -18,7 +18,8 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbanksr_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml
openfpga_vpr_device_layout=
openfpga_fast_configuration=