riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[HDL] Fixed critical bugs in multi-mode FF HDL modeling, which caused reset signal unconnected

This commit is contained in:
tangxifan 2021-10-30 11:45:01 -07:00
parent 9c06041ce4
commit 0a449cc24c
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
openfpga_flow/openfpga_cell_library/verilog/dff.v
View File

@ -260,7 +260,7 @@ module MULTI_MODE_DFFSRQ (
);
wire post_set = mode[1] ? ~SET : SET;
wire post_reset = mode[0] ? ~RST : RST;
wire post_rst = mode[0] ? ~RST : RST;
DFFSRQ FF_CORE (.SET(post_set),
.RST(post_rst),
@ -284,7 +284,7 @@ module MULTI_MODE_DFFRQ (
input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
);
wire post_reset = mode ? ~RST : RST;
wire post_rst = mode ? ~RST : RST;
DFFRQ FF_CORE (.RST(post_rst),
.CK(CK),