[HDL] Add multi-mode DFF module

openfpga_flow/openfpga_cell_library/verilog/dff.v

@@ -289,6 +289,34 @@ assign Q = q_reg;
 
 endmodule //End Of Module
 
+//-----------------------------------------------------
+// Function : A multi-functional D-type flip-flop with 
+//           - asynchronous reset 
+//             which can be switched between active-low and active hight
+//           - asynchronous set which can be switched 
+//             which can be switched between active-low and active hight
+//-----------------------------------------------------
+module MULTIMODE_DFFSRQ (
+  input SET, // Set input
+  input RST, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity
+);
+
+wire post_set = mode ? ~SET : SET;
+wire post_reset = mode ? ~RST : RST;
+
+DFFSRQ FF_CORE (.SET(post_set),
+                .RST(post_rst),
+                .CK(CK),
+                .D(D),
+                .Q(Q)
+               );
+
+endmodule //End Of Module
+
 //-----------------------------------------------------
 // Function    : D-type flip-flop with 
 //               - asynchronous active high reset