tangxifan
|
2bd60dad11
|
[script] now timing extraction focus on the last found results
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2023-12-12 14:10:13 -08:00 |
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tangxifan
|
592e2e310c
|
[script] typo
|
2023-12-12 13:45:23 -08:00 |
|
tangxifan
|
b182b47d0b
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[test] use a timing-focus tool path for a testcase
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2023-12-12 13:28:35 -08:00 |
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tangxifan
|
c5cc05a9f5
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[script] add a new example default tool path config with a focus on timing
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2023-12-12 13:22:50 -08:00 |
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tangxifan
|
f689ef7654
|
[script] format
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2023-12-12 13:15:03 -08:00 |
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tangxifan
|
4c0f6e2273
|
[script] syntax
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2023-12-12 13:14:47 -08:00 |
|
tangxifan
|
e753e6d22c
|
[script] syntax
|
2023-12-12 13:13:51 -08:00 |
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tangxifan
|
d9db78ac30
|
[script] now run fpga task has a new option ``default_tool_path``
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2023-12-12 13:11:48 -08:00 |
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tangxifan
|
1a4aaaf759
|
[script] update openfpga flow to support args for default tool path
|
2023-12-12 10:00:50 -08:00 |
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tangxifan
|
a7b22163a8
|
[script] fixe the mismatch on keywords against latest vpr
|
2023-12-12 09:52:42 -08:00 |
|
tangxifan
|
5c839c1858
|
[test] debug
|
2023-12-08 13:52:52 -08:00 |
|
tangxifan
|
6a5df804b9
|
[test] add new testcase to reg test
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2023-12-08 13:46:54 -08:00 |
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tangxifan
|
99f1c5493c
|
[test] add a new testcase to support vcs
|
2023-12-08 13:45:23 -08:00 |
Yitian4Debug
|
a1169beaf0
|
Update rst_on_lut_repack_dc.xml by changing the separator from , to . between pb type and pin name
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
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2023-12-04 13:34:49 -08:00 |
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Yitian4Debug
|
7475a002b6
|
Update repack_design_constraints.xml by changing the separater between pb type and pin name
To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
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2023-12-04 13:33:55 -08:00 |
ubuntu
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6055a42196
|
add test case
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2023-12-01 03:04:32 -08:00 |
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tangxifan
|
dff03e7993
|
[test] enable missing options in the arch used by benchmark sweeping tests
|
2023-11-14 09:45:02 -08:00 |
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tangxifan
|
0b473e3454
|
[test] fixed the bug in single-mode lut testcase
|
2023-11-14 09:35:26 -08:00 |
|
tangxifan
|
d108284105
|
[test] update arch to keep golden outputs
|
2023-11-14 09:31:07 -08:00 |
|
tangxifan
|
913434b70d
|
[test] fixed the bug that golden netlists are modified
|
2023-11-14 09:28:57 -08:00 |
|
tangxifan
|
59d086a27f
|
[test] try to keep the golden inputs
|
2023-11-14 09:25:45 -08:00 |
|
tangxifan
|
1b8748abb4
|
[core] update vtr
|
2023-11-13 14:21:34 -08:00 |
|
tangxifan
|
d78f18d235
|
[test] add new testcase
|
2023-11-13 14:11:34 -08:00 |
|
tangxifan
|
8e875f3453
|
[test] add a new test case to validate the new feature
|
2023-11-02 21:08:36 -07:00 |
|
tangxifan
|
c6f33bcd7f
|
[test] add new tests to cover the new features
|
2023-10-06 18:41:57 -07:00 |
|
tangxifan
|
7d83fc914c
|
[core] ad a new test case
|
2023-10-06 18:31:54 -07:00 |
|
tangxifan
|
5aa206e616
|
[core] fixed some bugs
|
2023-09-25 22:27:24 -07:00 |
|
tangxifan
|
60b8c396dc
|
[test] add a new test
|
2023-09-25 21:25:21 -07:00 |
|
tangxifan
|
a4f53c64c6
|
[test] fixed a bug
|
2023-09-25 19:28:19 -07:00 |
|
tangxifan
|
663c9c9fa1
|
[test] add a new test to validate the tile port merge feature
|
2023-09-25 18:34:34 -07:00 |
|
tangxifan
|
a1ed277a88
|
[test] typo
|
2023-09-23 15:12:02 -07:00 |
|
tangxifan
|
00e1a5df11
|
[test] fixed some bugs
|
2023-09-23 12:44:47 -07:00 |
|
tangxifan
|
195aa7a9a8
|
[test] developing new test to increase coverage on module renaming
|
2023-09-23 12:40:20 -07:00 |
|
tangxifan
|
f3279bd885
|
[test] now use 4x4 fabric to check the using index netlists
|
2023-09-20 22:49:47 -07:00 |
|
tangxifan
|
eeb1bd6662
|
[core] fixed some bugs
|
2023-09-17 23:16:15 -07:00 |
|
tangxifan
|
3fd60a165d
|
[test] typo
|
2023-09-17 17:42:15 -07:00 |
|
tangxifan
|
11e976ec92
|
[test] add a new test to validate renaming on fpga top/core modules
|
2023-09-17 17:38:37 -07:00 |
|
tangxifan
|
0ef1e0bde5
|
[test] add a new test to validate renaming rules
|
2023-09-17 13:29:12 -07:00 |
|
tangxifan
|
559fa45d89
|
[test] add a new test to validate module renaming using index
|
2023-09-16 17:55:52 -07:00 |
|
tangxifan
|
1287097ce5
|
[test] update golden netlists
|
2023-09-06 22:51:38 -07:00 |
|
tangxifan
|
401f8098a6
|
[test] update golden copies
|
2023-09-06 17:35:03 -07:00 |
|
tangxifan
|
db0bb291c2
|
[test] update settings
|
2023-08-22 15:22:48 -07:00 |
|
tangxifan
|
56cedf6c8b
|
[test] added a new test case to validate the support on different wire segment distribution on X and Y
|
2023-08-22 11:20:14 -07:00 |
|
tangxifan
|
1b132fd667
|
[test] add a new testcase to validate the support on different routing channel width on X and Y
|
2023-08-22 11:06:12 -07:00 |
|
tangxifan
|
15a8d8a76a
|
[test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation
|
2023-08-18 21:59:06 -07:00 |
|
tangxifan
|
5f6050d404
|
[test] add a new test to validate combo: group tile, tile annotation and subtile
|
2023-08-18 21:48:40 -07:00 |
|
tangxifan
|
e4c5265b68
|
[test] arch syntax
|
2023-08-18 21:40:56 -07:00 |
|
tangxifan
|
5ac8919ce0
|
[test] add a new testcase to validate subtile with tile annotations
|
2023-08-18 21:37:15 -07:00 |
|
tangxifan
|
f69520d0c3
|
[arch] format
|
2023-08-18 11:15:25 -07:00 |
|
tangxifan
|
170a49c34f
|
[test] fix a bug in arch file
|
2023-08-18 11:15:05 -07:00 |