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[core] update vtr

This commit is contained in:
tangxifan 2023-11-13 14:21:34 -08:00
parent d78f18d235
commit 1b8748abb4
2 changed files with 2 additions and 2 deletions
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2
openfpga_flow/vpr_arch/k6_frac_N10_tileableConcatWire_adder_chain_dpram8K_dsp36_fracff_40nm.xml
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@ -302,7 +302,7 @@
</tiles>
<!-- ODIN II specific config ends -->
<!-- Physical descriptions begin -->
<layout tileable="true" through_channel="false" concat_wire="true" concat_pass_wire="false">
<layout tileable="true" through_channel="false" opin2all_sides="true" concat_wire="true" concat_pass_wire="false">
<auto_layout aspect_ratio="1.0">
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
<perimeter type="io" priority="100"/>

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit 5d41e33cc89a34d0481550728f855252a63ac704
Subproject commit 229e43e30bd7a99bf34239179ad957ca6e00f8da