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[test] add a new test to validate renaming on fpga top/core modules

This commit is contained in:
tangxifan 2023-09-17 17:38:37 -07:00
parent 4ccb4737be
commit 11e976ec92
4 changed files with 59 additions and 0 deletions
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1
openfpga_flow/regression_test_scripts/basic_reg_test.sh
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@ -205,6 +205,7 @@ run-task basic_tests/group_config_block/group_config_block_homo_fabric_tile_glob
echo -e "Module naming";
run-task basic_tests/module_naming/using_index $@
run-task basic_tests/module_naming/renaming_rules $@
run-task basic_tests/module_naming/renaming_rules_strong $@
echo -e "Testing global port definition from tiles";
run-task basic_tests/global_tile_ports/global_tile_clock $@

6
openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_strong/config/module_names.xml Normal file
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@ -0,0 +1,6 @@
<module_names>
<module_name default="tile_1__1_" given="tile_clb"/>
<module_name default="tile_2__1_" given="tile_dsp"/>
<module_name default="fpga_core" given="pfabric_top"/>
<module_name default="fpga_top" given="pfabric_top"/>
</module_names>

51
openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_strong/config/task.conf Normal file
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@ -0,0 +1,51 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/module_rename_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=--constant_net_method route --skip_sync_clustering_and_routing_results on
openfpga_pb_pin_fixup_command = pb_pin_fixup --verbose
openfpga_vpr_device=3x2
openfpga_vpr_route_chan_width=60
openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=
openfpga_add_fpga_core_module=add_fpga_core_to_fabric --instance_name fpga_core_inst
openfpga_fabric_module_name_options=
openfpga_rename_module_file = ${PATH:TASK_DIR}/config/module_names.xml
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v
bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v
bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = mac_8
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/basic_tests/module_naming/renaming_rules_strong/config/tile_config.xml Normal file
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@ -0,0 +1 @@
<tiles style="top_left"/>