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OpenFPGA
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[core] code format

This commit is contained in:
tangxifan 2023-09-17 17:33:10 -07:00
parent f79da76656
commit 4ccb4737be
21 changed files with 164 additions and 178 deletions
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9
openfpga/src/base/openfpga_verilog_template.h
View File

@ -138,8 +138,7 @@ int write_full_testbench_template(const T& openfpga_ctx, const Command& cmd,
g_vpr_ctx.atom(), g_vpr_ctx.placement(), pin_constraints, bus_group,
cmd_context.option_value(cmd, opt_bitstream),
openfpga_ctx.io_location_map(), openfpga_ctx.io_name_map(),
openfpga_ctx.module_name_map(),
openfpga_ctx.fabric_global_port_info(),
openfpga_ctx.module_name_map(), openfpga_ctx.fabric_global_port_info(),
openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib,
openfpga_ctx.simulation_setting(), openfpga_ctx.arch().config_protocol,
options);
@ -213,8 +212,7 @@ int write_preconfigured_fabric_wrapper_template(
openfpga_ctx.module_graph(), openfpga_ctx.bitstream_manager(),
g_vpr_ctx.atom(), g_vpr_ctx.placement(), pin_constraints, bus_group,
openfpga_ctx.io_location_map(), openfpga_ctx.io_name_map(),
openfpga_ctx.module_name_map(),
openfpga_ctx.fabric_global_port_info(),
openfpga_ctx.module_name_map(), openfpga_ctx.fabric_global_port_info(),
openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib,
openfpga_ctx.arch().config_protocol, options);
}
@ -275,7 +273,8 @@ int write_mock_fpga_wrapper_template(const T& openfpga_ctx, const Command& cmd,
return fpga_verilog_mock_fpga_wrapper(
openfpga_ctx.module_graph(), g_vpr_ctx.atom(), g_vpr_ctx.placement(),
pin_constraints, bus_group, openfpga_ctx.io_location_map(),
openfpga_ctx.io_name_map(), openfpga_ctx.module_name_map(), openfpga_ctx.fabric_global_port_info(),
openfpga_ctx.io_name_map(), openfpga_ctx.module_name_map(),
openfpga_ctx.fabric_global_port_info(),
openfpga_ctx.vpr_netlist_annotation(), options);
}

29
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -105,7 +105,8 @@ int fpga_fabric_verilog(
* logic generation is not possible!!!
*/
print_verilog_submodule(module_manager, netlist_manager, blwl_sr_banks,
mux_lib, decoder_lib, circuit_lib, module_name_map, submodule_dir_path,
mux_lib, decoder_lib, circuit_lib, module_name_map,
submodule_dir_path,
std::string(DEFAULT_SUBMODULE_DIR_NAME), options);
/* Generate routing blocks */
@ -142,12 +143,10 @@ int fpga_fabric_verilog(
/* Generate FPGA fabric */
print_verilog_core_module(netlist_manager,
const_cast<const ModuleManager &>(module_manager),
module_name_map,
src_dir_path, options);
module_name_map, src_dir_path, options);
print_verilog_top_module(netlist_manager,
const_cast<const ModuleManager &>(module_manager),
module_name_map,
src_dir_path, options);
module_name_map, src_dir_path, options);
/* Generate an netlist including all the fabric-related netlists */
print_verilog_fabric_include_netlist(
@ -176,8 +175,7 @@ int fpga_verilog_full_testbench(
const AtomContext &atom_ctx, const PlacementContext &place_ctx,
const PinConstraints &pin_constraints, const BusGroup &bus_group,
const std::string &bitstream_file, const IoLocationMap &io_location_map,
const IoNameMap &io_name_map,
const ModuleNameMap& module_name_map,
const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
const FabricGlobalPortInfo &fabric_global_port_info,
const VprNetlistAnnotation &netlist_annotation,
const CircuitLibrary &circuit_lib,
@ -205,8 +203,7 @@ int fpga_verilog_full_testbench(
module_manager, bitstream_manager, fabric_bitstream, blwl_sr_banks,
circuit_lib, config_protocol, fabric_global_port_info, atom_ctx, place_ctx,
pin_constraints, bus_group, bitstream_file, io_location_map, io_name_map,
module_name_map,
netlist_annotation, netlist_name, top_testbench_file_path,
module_name_map, netlist_annotation, netlist_name, top_testbench_file_path,
simulation_setting, options);
/* Generate a Verilog file including all the netlists that have been generated
@ -228,8 +225,7 @@ int fpga_verilog_preconfigured_fabric_wrapper(
const BitstreamManager &bitstream_manager, const AtomContext &atom_ctx,
const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
const BusGroup &bus_group, const IoLocationMap &io_location_map,
const IoNameMap &io_name_map,
const ModuleNameMap &module_name_map,
const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
const FabricGlobalPortInfo &fabric_global_port_info,
const VprNetlistAnnotation &netlist_annotation,
const CircuitLibrary &circuit_lib, const ConfigProtocol &config_protocol,
@ -254,8 +250,8 @@ int fpga_verilog_preconfigured_fabric_wrapper(
status = print_verilog_preconfig_top_module(
module_manager, bitstream_manager, config_protocol, circuit_lib,
fabric_global_port_info, atom_ctx, place_ctx, pin_constraints, bus_group,
io_location_map, io_name_map, module_name_map, netlist_annotation, netlist_name,
formal_verification_top_netlist_file_path, options);
io_location_map, io_name_map, module_name_map, netlist_annotation,
netlist_name, formal_verification_top_netlist_file_path, options);
return status;
}
@ -268,8 +264,7 @@ int fpga_verilog_mock_fpga_wrapper(
const ModuleManager &module_manager, const AtomContext &atom_ctx,
const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
const BusGroup &bus_group, const IoLocationMap &io_location_map,
const IoNameMap &io_name_map,
const ModuleNameMap &module_name_map,
const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
const FabricGlobalPortInfo &fabric_global_port_info,
const VprNetlistAnnotation &netlist_annotation,
const VerilogTestbenchOption &options) {
@ -294,8 +289,8 @@ int fpga_verilog_mock_fpga_wrapper(
std::string netlist_file_path = src_dir_path + netlist_file_name;
status = print_verilog_mock_fpga_wrapper(
module_manager, fabric_global_port_info, atom_ctx, place_ctx,
pin_constraints, bus_group, io_location_map, io_name_map,
module_name_map, netlist_annotation, netlist_name, netlist_file_path, options);
pin_constraints, bus_group, io_location_map, io_name_map, module_name_map,
netlist_annotation, netlist_name, netlist_file_path, options);
/* Add fname to the netlist name list */
NetlistId nlist_id = NetlistId::INVALID();

9
openfpga/src/fpga_verilog/verilog_api.h
View File

@ -56,8 +56,7 @@ int fpga_verilog_full_testbench(
const AtomContext& atom_ctx, const PlacementContext& place_ctx,
const PinConstraints& pin_constraints, const BusGroup& bus_group,
const std::string& bitstream_file, const IoLocationMap& io_location_map,
const IoNameMap& io_name_map,
const ModuleNameMap& module_name_map,
const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
const FabricGlobalPortInfo& fabric_global_port_info,
const VprNetlistAnnotation& netlist_annotation,
const CircuitLibrary& circuit_lib,
@ -69,8 +68,7 @@ int fpga_verilog_preconfigured_fabric_wrapper(
const BitstreamManager& bitstream_manager, const AtomContext& atom_ctx,
const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
const BusGroup& bus_group, const IoLocationMap& io_location_map,
const IoNameMap& io_name_map,
const ModuleNameMap& module_name_map,
const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
const FabricGlobalPortInfo& fabric_global_port_info,
const VprNetlistAnnotation& netlist_annotation,
const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
@ -80,8 +78,7 @@ int fpga_verilog_mock_fpga_wrapper(
const ModuleManager& module_manager, const AtomContext& atom_ctx,
const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
const BusGroup& bus_group, const IoLocationMap& io_location_map,
const IoNameMap& io_name_map,
const ModuleNameMap& module_name_map,
const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
const FabricGlobalPortInfo& fabric_global_port_info,
const VprNetlistAnnotation& netlist_annotation,
const VerilogTestbenchOption& options);

30
openfpga/src/fpga_verilog/verilog_decoders.cpp
View File

@ -52,8 +52,8 @@ static void print_verilog_mux_local_decoder_module(
VTR_ASSERT(true == valid_file_stream(fp));
/* TODO: create a name for the local encoder */
std::string module_name =
module_name_map.name(generate_mux_local_decoder_subckt_name(addr_size, data_size));
std::string module_name = module_name_map.name(
generate_mux_local_decoder_subckt_name(addr_size, data_size));
/* Create a Verilog Module based on the circuit model, and add to module
* manager */
@ -181,9 +181,8 @@ static void print_verilog_mux_local_decoder_module(
void print_verilog_submodule_mux_local_decoders(
const ModuleManager& module_manager, NetlistManager& netlist_manager,
const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map,
const std::string& submodule_dir, const std::string& submodule_dir_name,
const FabricVerilogOption& options) {
const ModuleNameMap& module_name_map, const std::string& submodule_dir,
const std::string& submodule_dir_name, const FabricVerilogOption& options) {
std::string verilog_fname(LOCAL_ENCODER_VERILOG_FILE_NAME);
std::string verilog_fpath(submodule_dir + verilog_fname);
@ -237,7 +236,8 @@ void print_verilog_submodule_mux_local_decoders(
/* Generate Verilog modules for the found unique local encoders */
for (const auto& decoder : decoder_lib.decoders()) {
print_verilog_mux_local_decoder_module(fp, module_manager, decoder_lib,
decoder, module_name_map, options.default_net_type());
decoder, module_name_map,
options.default_net_type());
}
/* Close the file stream */
@ -292,8 +292,8 @@ static void print_verilog_arch_decoder_module(
VTR_ASSERT(true == valid_file_stream(fp));
/* Create a name for the decoder */
std::string module_name =
module_name_map.name(generate_memory_decoder_subckt_name(addr_size, data_size));
std::string module_name = module_name_map.name(
generate_memory_decoder_subckt_name(addr_size, data_size));
/* Create a Verilog Module based on the circuit model, and add to module
* manager */
@ -617,8 +617,8 @@ static void print_verilog_arch_decoder_with_data_in_module(
VTR_ASSERT(true == valid_file_stream(fp));
/* Create a name for the decoder */
std::string module_name =
module_name_map.name(generate_memory_decoder_with_data_in_subckt_name(addr_size, data_size));
std::string module_name = module_name_map.name(
generate_memory_decoder_with_data_in_subckt_name(addr_size, data_size));
/* Create a Verilog Module based on the circuit model, and add to module
* manager */
@ -783,8 +783,8 @@ static void print_verilog_arch_decoder_with_data_in_module(
void print_verilog_submodule_arch_decoders(
const ModuleManager& module_manager, NetlistManager& netlist_manager,
const DecoderLibrary& decoder_lib, const ModuleNameMap& module_name_map,
const std::string& submodule_dir,
const std::string& submodule_dir_name, const FabricVerilogOption& options) {
const std::string& submodule_dir, const std::string& submodule_dir_name,
const FabricVerilogOption& options) {
std::string verilog_fname(ARCH_ENCODER_VERILOG_FILE_NAME);
std::string verilog_fpath(submodule_dir + verilog_fname);
@ -806,10 +806,12 @@ void print_verilog_submodule_arch_decoders(
for (const auto& decoder : decoder_lib.decoders()) {
if (true == decoder_lib.use_data_in(decoder)) {
print_verilog_arch_decoder_with_data_in_module(
fp, module_manager, decoder_lib, decoder, module_name_map, options.default_net_type());
fp, module_manager, decoder_lib, decoder, module_name_map,
options.default_net_type());
} else {
print_verilog_arch_decoder_module(fp, module_manager, decoder_lib,
decoder, module_name_map, options.default_net_type());
decoder, module_name_map,
options.default_net_type());
}
}

9
openfpga/src/fpga_verilog/verilog_decoders.h
View File

@ -28,15 +28,14 @@ namespace openfpga {
void print_verilog_submodule_mux_local_decoders(
const ModuleManager& module_manager, NetlistManager& netlist_manager,
const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map,
const std::string& submodule_dir, const std::string& submodule_dir_name,
const FabricVerilogOption& options);
const ModuleNameMap& module_name_map, const std::string& submodule_dir,
const std::string& submodule_dir_name, const FabricVerilogOption& options);
void print_verilog_submodule_arch_decoders(
const ModuleManager& module_manager, NetlistManager& netlist_manager,
const DecoderLibrary& decoder_lib, const ModuleNameMap& module_name_map,
const std::string& submodule_dir,
const std::string& submodule_dir_name, const FabricVerilogOption& options);
const std::string& submodule_dir, const std::string& submodule_dir_name,
const FabricVerilogOption& options);
} /* end namespace openfpga */

32
openfpga/src/fpga_verilog/verilog_essential_gates.cpp
View File

@ -176,8 +176,8 @@ static void print_verilog_invbuf_module(
/* Create a Verilog Module based on the circuit model, and add to module
* manager */
ModuleId module_id =
module_manager.find_module(module_name_map.name(circuit_lib.model_name(circuit_model)));
ModuleId module_id = module_manager.find_module(
module_name_map.name(circuit_lib.model_name(circuit_model)));
VTR_ASSERT(true == module_manager.valid_module_id(module_id));
/* dump module definition + ports */
@ -272,8 +272,8 @@ static void print_verilog_passgate_module(
/* Create a Verilog Module based on the circuit model, and add to module
* manager */
ModuleId module_id =
module_manager.find_module(module_name_map.name(circuit_lib.model_name(circuit_model)));
ModuleId module_id = module_manager.find_module(
module_name_map.name(circuit_lib.model_name(circuit_model)));
VTR_ASSERT(true == module_manager.valid_module_id(module_id));
/* dump module definition + ports */
@ -468,8 +468,8 @@ static void print_verilog_gate_module(
/* Create a Verilog Module based on the circuit model, and add to module
* manager */
ModuleId module_id =
module_manager.find_module(module_name_map.name(circuit_lib.model_name(circuit_model)));
ModuleId module_id = module_manager.find_module(
module_name_map.name(circuit_lib.model_name(circuit_model)));
VTR_ASSERT(true == module_manager.valid_module_id(module_id));
/* dump module definition + ports */
@ -509,12 +509,12 @@ static void print_verilog_gate_module(
***********************************************/
static void print_verilog_constant_generator_module(
const ModuleManager& module_manager, std::fstream& fp,
const size_t& const_value,
const ModuleNameMap& module_name_map,
const size_t& const_value, const ModuleNameMap& module_name_map,
const e_verilog_default_net_type& default_net_type) {
/* Find the module in module manager */
std::string module_name = generate_const_value_module_name(const_value);
ModuleId const_val_module = module_manager.find_module(module_name_map.name(module_name));
ModuleId const_val_module =
module_manager.find_module(module_name_map.name(module_name));
VTR_ASSERT(true == module_manager.valid_module_id(const_val_module));
/* Ensure a valid file handler*/
@ -568,11 +568,11 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
/* Print constant generators */
/* VDD */
print_verilog_constant_generator_module(module_manager, fp, 0,
module_name_map, options.default_net_type());
print_verilog_constant_generator_module(
module_manager, fp, 0, module_name_map, options.default_net_type());
/* GND */
print_verilog_constant_generator_module(module_manager, fp, 1,
module_name_map, options.default_net_type());
print_verilog_constant_generator_module(
module_manager, fp, 1, module_name_map, options.default_net_type());
for (const auto& circuit_model : circuit_lib.models()) {
/* By pass user-defined modules */
@ -581,12 +581,14 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
}
if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
print_verilog_invbuf_module(module_manager, fp, circuit_lib,
circuit_model, module_name_map, options.default_net_type());
circuit_model, module_name_map,
options.default_net_type());
continue;
}
if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) {
print_verilog_passgate_module(module_manager, fp, circuit_lib,
circuit_model, module_name_map, options.default_net_type());
circuit_model, module_name_map,
options.default_net_type());
continue;
}
if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model)) {

53
openfpga/src/fpga_verilog/verilog_grid.cpp
View File

@ -66,10 +66,9 @@ namespace openfpga {
*******************************************************************/
static void print_verilog_primitive_block(
NetlistManager& netlist_manager, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const std::string& subckt_dir, const std::string& subckt_dir_name,
t_pb_graph_node* primitive_pb_graph_node, const FabricVerilogOption& options,
const bool& verbose) {
const ModuleNameMap& module_name_map, const std::string& subckt_dir,
const std::string& subckt_dir_name, t_pb_graph_node* primitive_pb_graph_node,
const FabricVerilogOption& options, const bool& verbose) {
/* Ensure a valid pb_graph_node */
if (nullptr == primitive_pb_graph_node) {
VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid primitive_pb_graph_node!\n");
@ -175,8 +174,8 @@ static void rec_print_verilog_logical_tile(
for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
/* Go recursive to visit the children */
rec_print_verilog_logical_tile(
netlist_manager, module_manager, module_name_map, device_annotation, subckt_dir,
subckt_dir_name,
netlist_manager, module_manager, module_name_map, device_annotation,
subckt_dir, subckt_dir_name,
&(physical_pb_graph_node
->child_pb_graph_nodes[physical_mode->index][ipb][0]),
options, verbose);
@ -185,9 +184,9 @@ static void rec_print_verilog_logical_tile(
/* For leaf node, a primitive Verilog module will be generated. */
if (true == is_primitive_pb_type(physical_pb_type)) {
print_verilog_primitive_block(netlist_manager, module_manager, module_name_map, subckt_dir,
subckt_dir_name, physical_pb_graph_node,
options, verbose);
print_verilog_primitive_block(netlist_manager, module_manager,
module_name_map, subckt_dir, subckt_dir_name,
physical_pb_graph_node, options, verbose);
/* Finish for primitive node, return */
return;
}
@ -281,9 +280,9 @@ static void print_verilog_logical_tile_netlist(
*/
/* Print Verilog modules starting from the top-level pb_type/pb_graph_node,
* and traverse the graph in a recursive way */
rec_print_verilog_logical_tile(netlist_manager, module_manager, module_name_map,
device_annotation, subckt_dir, subckt_dir_name,
pb_graph_head, options, verbose);
rec_print_verilog_logical_tile(
netlist_manager, module_manager, module_name_map, device_annotation,
subckt_dir, subckt_dir_name, pb_graph_head, options, verbose);
VTR_LOG("Done\n");
VTR_LOG("\n");
@ -299,10 +298,9 @@ static void print_verilog_logical_tile_netlist(
*****************************************************************************/
static void print_verilog_physical_tile_netlist(
NetlistManager& netlist_manager, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const std::string& subckt_dir, const std::string& subckt_dir_name,
t_physical_tile_type_ptr phy_block_type, const e_side& border_side,
const FabricVerilogOption& options) {
const ModuleNameMap& module_name_map, const std::string& subckt_dir,
const std::string& subckt_dir_name, t_physical_tile_type_ptr phy_block_type,
const e_side& border_side, const FabricVerilogOption& options) {
/* Give a name to the Verilog netlist */
std::string verilog_fname(generate_grid_block_netlist_name(
std::string(GRID_MODULE_NAME_PREFIX) + std::string(phy_block_type->name),
@ -384,10 +382,10 @@ static void print_verilog_physical_tile_netlist(
****************************************************************************/
void print_verilog_grids(
NetlistManager& netlist_manager, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation,
const std::string& subckt_dir, const std::string& subckt_dir_name,
const FabricVerilogOption& options, const bool& verbose) {
const ModuleNameMap& module_name_map, const DeviceContext& device_ctx,
const VprDeviceAnnotation& device_annotation, const std::string& subckt_dir,
const std::string& subckt_dir_name, const FabricVerilogOption& options,
const bool& verbose) {
/* Create a vector to contain all the Verilog netlist names that have been
* generated in this function */
std::vector<std::string> netlist_names;
@ -408,8 +406,9 @@ void print_verilog_grids(
continue;
}
print_verilog_logical_tile_netlist(
netlist_manager, module_manager, module_name_map, device_annotation, subckt_dir,
subckt_dir_name, logical_tile.pb_graph_head, options, verbose);
netlist_manager, module_manager, module_name_map, device_annotation,
subckt_dir, subckt_dir_name, logical_tile.pb_graph_head, options,
verbose);
}
VTR_LOG("Writing logical tiles...");
VTR_LOG("Done\n");
@ -440,15 +439,15 @@ void print_verilog_grids(
find_physical_io_tile_located_sides(device_ctx.grid, &physical_tile);
for (const e_side& io_type_side : io_type_sides) {
print_verilog_physical_tile_netlist(
netlist_manager, module_manager, module_name_map, subckt_dir, subckt_dir_name,
&physical_tile, io_type_side, options);
netlist_manager, module_manager, module_name_map, subckt_dir,
subckt_dir_name, &physical_tile, io_type_side, options);
}
continue;
} else {
/* For CLB and heterogenenous blocks */
print_verilog_physical_tile_netlist(netlist_manager, module_manager,
module_name_map, subckt_dir, subckt_dir_name,
&physical_tile, NUM_SIDES, options);
print_verilog_physical_tile_netlist(
netlist_manager, module_manager, module_name_map, subckt_dir,
subckt_dir_name, &physical_tile, NUM_SIDES, options);
}
}
VTR_LOG("Building physical tiles...");

8
openfpga/src/fpga_verilog/verilog_grid.h
View File

@ -22,10 +22,10 @@ namespace openfpga {
void print_verilog_grids(
NetlistManager& netlist_manager, const ModuleManager& module_manager,
const ModuleNameMap& module_name_map,
const DeviceContext& device_ctx, const VprDeviceAnnotation& device_annotation,
const std::string& subckt_dir, const std::string& subckt_dir_name,
const FabricVerilogOption& options, const bool& verbose);
const ModuleNameMap& module_name_map, const DeviceContext& device_ctx,
const VprDeviceAnnotation& device_annotation, const std::string& subckt_dir,
const std::string& subckt_dir_name, const FabricVerilogOption& options,
const bool& verbose);
} /* end namespace openfpga */

4
openfpga/src/fpga_verilog/verilog_lut.cpp
View File

@ -56,8 +56,8 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
continue;
}
/* Find the module id */
ModuleId lut_module =
module_manager.find_module(module_name_map.name(circuit_lib.model_name(lut_model)));
ModuleId lut_module = module_manager.find_module(
module_name_map.name(circuit_lib.model_name(lut_model)));
VTR_ASSERT(true == module_manager.valid_module_id(lut_module));
write_verilog_module_to_file(
fp, module_manager, lut_module,

16
openfpga/src/fpga_verilog/verilog_memory.cpp
View File

@ -42,8 +42,7 @@ namespace openfpga {
static void print_verilog_mux_memory_module(
const ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph,
const ModuleNameMap& module_name_map,
const FabricVerilogOption& options) {
const ModuleNameMap& module_name_map, const FabricVerilogOption& options) {
/* Multiplexers built with different technology is in different organization
*/
switch (circuit_lib.design_tech_type(mux_model)) {
@ -121,14 +120,11 @@ static void print_verilog_mux_memory_module(
* Take another example, the memory circuit can implement the scan-chain or
* memory-bank organization for the memories.
********************************************************************/
void print_verilog_submodule_memories(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map,
const std::string& submodule_dir,
const std::string& submodule_dir_name,
const FabricVerilogOption& options) {
void print_verilog_submodule_memories(
const ModuleManager& module_manager, NetlistManager& netlist_manager,
const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map, const std::string& submodule_dir,
const std::string& submodule_dir_name, const FabricVerilogOption& options) {
/* Plug in with the mux subckt */
std::string verilog_fname(MEMORIES_VERILOG_FILE_NAME);
std::string verilog_fpath(submodule_dir + verilog_fname);

13
openfpga/src/fpga_verilog/verilog_memory.h
View File

@ -21,14 +21,11 @@
/* begin namespace openfpga */
namespace openfpga {
void print_verilog_submodule_memories(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map,
const std::string& submodule_dir,
const std::string& submodule_dir_name,
const FabricVerilogOption& options);
void print_verilog_submodule_memories(
const ModuleManager& module_manager, NetlistManager& netlist_manager,
const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map, const std::string& submodule_dir,
const std::string& submodule_dir_name, const FabricVerilogOption& options);
} /* end namespace openfpga */

7
openfpga/src/fpga_verilog/verilog_mock_fpga_wrapper.cpp
View File

@ -473,7 +473,8 @@ int print_verilog_mock_fpga_wrapper(
print_verilog_file_header(fp, title, options.time_stamp());
/* Find the top_module */
ModuleId top_module = module_manager.find_module(module_name_map.name(options.dut_module()));
ModuleId top_module =
module_manager.find_module(module_name_map.name(options.dut_module()));
if (!module_manager.valid_module_id(top_module)) {
VTR_LOG_ERROR(
"Unable to find the DUT module '%s'. Please check if you create "
@ -484,8 +485,8 @@ int print_verilog_mock_fpga_wrapper(
/* Note that we always need the core module as it contains the original port
* names before possible renaming at top-level module. If there is no core
* module, it means that the current top module is the core module */
ModuleId core_module =
module_manager.find_module(module_name_map.name(generate_fpga_core_module_name()));
ModuleId core_module = module_manager.find_module(
module_name_map.name(generate_fpga_core_module_name()));
if (!module_manager.valid_module_id(core_module)) {
core_module = top_module;
}

54
openfpga/src/fpga_verilog/verilog_mux.cpp
View File

@ -643,8 +643,7 @@ static void generate_verilog_rram_mux_branch_module(
static void generate_verilog_mux_branch_module(
ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph,
const ModuleNameMap& module_name_map,
const bool& use_explicit_port_map,
const ModuleNameMap& module_name_map, const bool& use_explicit_port_map,
const e_verilog_default_net_type& default_net_type,
std::map<std::string, bool>& branch_mux_module_is_outputted) {
std::string module_name = generate_mux_branch_subckt_name(
@ -1402,8 +1401,7 @@ static void generate_verilog_rram_mux_module(
static void generate_verilog_mux_module(
ModuleManager& module_manager, const CircuitLibrary& circuit_lib,
std::fstream& fp, const CircuitModelId& mux_model, const MuxGraph& mux_graph,
const ModuleNameMap& module_name_map,
const bool& use_explicit_port_map,
const ModuleNameMap& module_name_map, const bool& use_explicit_port_map,
const e_verilog_default_net_type& default_net_type) {
std::string module_name =
generate_mux_subckt_name(circuit_lib, mux_model,
@ -1451,9 +1449,8 @@ static void generate_verilog_mux_module(
static void print_verilog_submodule_mux_primitives(
ModuleManager& module_manager, NetlistManager& netlist_manager,
const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map,
const std::string& submodule_dir, const std::string& submodule_dir_name,
const FabricVerilogOption& options) {
const ModuleNameMap& module_name_map, const std::string& submodule_dir,
const std::string& submodule_dir_name, const FabricVerilogOption& options) {
/* Output primitive cells for MUX modules */
std::string verilog_fname(MUX_PRIMITIVES_VERILOG_FILE_NAME);
std::string verilog_fpath(submodule_dir + verilog_fname);
@ -1488,9 +1485,9 @@ static void print_verilog_submodule_mux_primitives(
/* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */
for (auto branch_mux_graph : branch_mux_graphs) {
generate_verilog_mux_branch_module(
module_manager, circuit_lib, fp, mux_circuit_model, branch_mux_graph, module_name_map,
options.explicit_port_mapping(), options.default_net_type(),
branch_mux_module_is_outputted);
module_manager, circuit_lib, fp, mux_circuit_model, branch_mux_graph,
module_name_map, options.explicit_port_mapping(),
options.default_net_type(), branch_mux_module_is_outputted);
}
}
@ -1517,9 +1514,8 @@ static void print_verilog_submodule_mux_primitives(
static void print_verilog_submodule_mux_top_modules(
ModuleManager& module_manager, NetlistManager& netlist_manager,
const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map,
const std::string& submodule_dir, const std::string& submodule_dir_name,
const FabricVerilogOption& options) {
const ModuleNameMap& module_name_map, const std::string& submodule_dir,
const std::string& submodule_dir_name, const FabricVerilogOption& options) {
/* Output top-level MUX modules */
std::string verilog_fname(MUXES_VERILOG_FILE_NAME);
std::string verilog_fpath(submodule_dir + verilog_fname);
@ -1542,9 +1538,10 @@ static void print_verilog_submodule_mux_top_modules(
const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux);
/* Create MUX circuits */
generate_verilog_mux_module(
module_manager, circuit_lib, fp, mux_circuit_model, mux_graph,
module_name_map, options.explicit_port_mapping(), options.default_net_type());
generate_verilog_mux_module(module_manager, circuit_lib, fp,
mux_circuit_model, mux_graph, module_name_map,
options.explicit_port_mapping(),
options.default_net_type());
}
/* Close the file stream */
@ -1572,21 +1569,18 @@ static void print_verilog_submodule_mux_top_modules(
* - A Verilog netlist contains all the top-level
* module for routing multiplexers
**********************************************/
void print_verilog_submodule_muxes(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map,
const std::string& submodule_dir,
const std::string& submodule_dir_name,
const FabricVerilogOption& options) {
print_verilog_submodule_mux_primitives(module_manager, netlist_manager,
mux_lib, circuit_lib, module_name_map, submodule_dir,
submodule_dir_name, options);
void print_verilog_submodule_muxes(
ModuleManager& module_manager, NetlistManager& netlist_manager,
const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map, const std::string& submodule_dir,
const std::string& submodule_dir_name, const FabricVerilogOption& options) {
print_verilog_submodule_mux_primitives(
module_manager, netlist_manager, mux_lib, circuit_lib, module_name_map,
submodule_dir, submodule_dir_name, options);
print_verilog_submodule_mux_top_modules(module_manager, netlist_manager,
mux_lib, circuit_lib, module_name_map, submodule_dir,
submodule_dir_name, options);
print_verilog_submodule_mux_top_modules(
module_manager, netlist_manager, mux_lib, circuit_lib, module_name_map,
submodule_dir, submodule_dir_name, options);
}
} /* end namespace openfpga */

13
openfpga/src/fpga_verilog/verilog_mux.h
View File

@ -22,14 +22,11 @@
/* begin namespace openfpga */
namespace openfpga {
void print_verilog_submodule_muxes(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map,
const std::string& submodule_dir,
const std::string& submodule_dir_name,
const FabricVerilogOption& options);
void print_verilog_submodule_muxes(
ModuleManager& module_manager, NetlistManager& netlist_manager,
const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map, const std::string& submodule_dir,
const std::string& submodule_dir_name, const FabricVerilogOption& options);
} /* end namespace openfpga */

9
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -540,7 +540,7 @@ int print_verilog_preconfig_top_module(
const FabricGlobalPortInfo &global_ports, const AtomContext &atom_ctx,
const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
const BusGroup &bus_group, const IoLocationMap &io_location_map,
const IoNameMap &io_name_map, const ModuleNameMap& module_name_map,
const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
const VprNetlistAnnotation &netlist_annotation,
const std::string &circuit_name, const std::string &verilog_fname,
const VerilogTestbenchOption &options) {
@ -574,7 +574,8 @@ int print_verilog_preconfig_top_module(
netlist_annotation, bus_group);
/* Spot the dut module */
ModuleId top_module = module_manager.find_module(module_name_map.name(options.dut_module()));
ModuleId top_module =
module_manager.find_module(module_name_map.name(options.dut_module()));
if (!module_manager.valid_module_id(top_module)) {
VTR_LOG_ERROR(
"Unable to find the DUT module '%s'. Please check if you create "
@ -585,8 +586,8 @@ int print_verilog_preconfig_top_module(
/* Note that we always need the core module as it contains the original port
* names before possible renaming at top-level module. If there is no core
* module, it means that the current top module is the core module */
ModuleId core_module =
module_manager.find_module(module_name_map.name(generate_fpga_core_module_name()));
ModuleId core_module = module_manager.find_module(
module_name_map.name(generate_fpga_core_module_name()));
if (!module_manager.valid_module_id(core_module)) {
core_module = top_module;
}

2
openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
View File

@ -14,8 +14,8 @@
#include "fabric_global_port_info.h"
#include "io_location_map.h"
#include "io_name_map.h"
#include "module_name_map.h"
#include "module_manager.h"
#include "module_name_map.h"
#include "pin_constraints.h"
#include "verilog_testbench_options.h"
#include "vpr_context.h"

28
openfpga/src/fpga_verilog/verilog_submodule.cpp
View File

@ -36,17 +36,19 @@ void print_verilog_submodule(
ModuleManager& module_manager, NetlistManager& netlist_manager,
const MemoryBankShiftRegisterBanks& blwl_sr_banks, const MuxLibrary& mux_lib,
const DecoderLibrary& decoder_lib, const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map,
const std::string& submodule_dir, const std::string& submodule_dir_name,
const ModuleNameMap& module_name_map, const std::string& submodule_dir,
const std::string& submodule_dir_name,
const FabricVerilogOption& fpga_verilog_opts) {
print_verilog_submodule_essentials(
const_cast<const ModuleManager&>(module_manager), netlist_manager,
submodule_dir, submodule_dir_name, circuit_lib, module_name_map, fpga_verilog_opts);
submodule_dir, submodule_dir_name, circuit_lib, module_name_map,
fpga_verilog_opts);
/* Decoders for architecture */
print_verilog_submodule_arch_decoders(
const_cast<const ModuleManager&>(module_manager), netlist_manager,
decoder_lib, module_name_map, submodule_dir, submodule_dir_name, fpga_verilog_opts);
decoder_lib, module_name_map, submodule_dir, submodule_dir_name,
fpga_verilog_opts);
/* Routing multiplexers */
/* NOTE: local decoders generation must go before the MUX generation!!!
@ -55,25 +57,29 @@ void print_verilog_submodule(
*/
print_verilog_submodule_mux_local_decoders(
const_cast<const ModuleManager&>(module_manager), netlist_manager, mux_lib,
circuit_lib, module_name_map, submodule_dir, submodule_dir_name, fpga_verilog_opts);
circuit_lib, module_name_map, submodule_dir, submodule_dir_name,
fpga_verilog_opts);
print_verilog_submodule_muxes(module_manager, netlist_manager, mux_lib,
circuit_lib, module_name_map, submodule_dir, submodule_dir_name,
fpga_verilog_opts);
circuit_lib, module_name_map, submodule_dir,
submodule_dir_name, fpga_verilog_opts);
/* LUTes */
print_verilog_submodule_luts(const_cast<const ModuleManager&>(module_manager),
netlist_manager, circuit_lib, module_name_map, submodule_dir,
submodule_dir_name, fpga_verilog_opts);
netlist_manager, circuit_lib, module_name_map,
submodule_dir, submodule_dir_name,
fpga_verilog_opts);
/* Hard wires */
print_verilog_submodule_wires(
const_cast<const ModuleManager&>(module_manager), netlist_manager,
circuit_lib, module_name_map, submodule_dir, submodule_dir_name, fpga_verilog_opts);
circuit_lib, module_name_map, submodule_dir, submodule_dir_name,
fpga_verilog_opts);
/* Memories */
print_verilog_submodule_memories(
const_cast<const ModuleManager&>(module_manager), netlist_manager, mux_lib,
circuit_lib, module_name_map, submodule_dir, submodule_dir_name, fpga_verilog_opts);
circuit_lib, module_name_map, submodule_dir, submodule_dir_name,
fpga_verilog_opts);
/* Shift register banks */
print_verilog_submodule_shift_register_banks(

4
openfpga/src/fpga_verilog/verilog_submodule.h
View File

@ -23,8 +23,8 @@ void print_verilog_submodule(
ModuleManager& module_manager, NetlistManager& netlist_manager,
const MemoryBankShiftRegisterBanks& blwl_sr_banks, const MuxLibrary& mux_lib,
const DecoderLibrary& decoder_lib, const CircuitLibrary& circuit_lib,
const ModuleNameMap& module_name_map,
const std::string& submodule_dir, const std::string& submodule_dir_name,
const ModuleNameMap& module_name_map, const std::string& submodule_dir,
const std::string& submodule_dir_name,
const FabricVerilogOption& fpga_verilog_opts);
} /* end namespace openfpga */

7
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -2478,7 +2478,8 @@ int print_verilog_full_testbench(
print_verilog_file_header(fp, title, options.time_stamp());
/* Spot the dut module */
ModuleId top_module = module_manager.find_module(module_name_map.name(options.dut_module()));
ModuleId top_module =
module_manager.find_module(module_name_map.name(options.dut_module()));
if (!module_manager.valid_module_id(top_module)) {
VTR_LOG_ERROR(
"Unable to find the DUT module '%s'. Please check if you create "
@ -2489,8 +2490,8 @@ int print_verilog_full_testbench(
/* Note that we always need the core module as it contains the original port
* names before possible renaming at top-level module. If there is no core
* module, it means that the current top module is the core module */
ModuleId core_module =
module_manager.find_module(module_name_map.name(generate_fpga_core_module_name()));
ModuleId core_module = module_manager.find_module(
module_name_map.name(generate_fpga_core_module_name()));
if (!module_manager.valid_module_id(core_module)) {
core_module = top_module;
}

2
openfpga/src/fpga_verilog/verilog_top_testbench.h
View File

@ -15,9 +15,9 @@
#include "fabric_global_port_info.h"
#include "io_location_map.h"
#include "io_name_map.h"
#include "module_name_map.h"
#include "memory_bank_shift_register_banks.h"
#include "module_manager.h"
#include "module_name_map.h"
#include "pin_constraints.h"
#include "simulation_setting.h"
#include "verilog_testbench_options.h"

4
openfpga/src/fpga_verilog/verilog_wire.cpp
View File

@ -56,8 +56,8 @@ static void print_verilog_wire_module(
/* Create a Verilog Module based on the circuit model, and add to module
* manager */
ModuleId wire_module =
module_manager.find_module(module_name_map.name(circuit_lib.model_name(wire_model)));
ModuleId wire_module = module_manager.find_module(
module_name_map.name(circuit_lib.model_name(wire_model)));
VTR_ASSERT(true == module_manager.valid_module_id(wire_module));
/* dump module definition + ports */