riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Update repack_design_constraints.xml by changing the separater between pb type and pin name 

To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
This commit is contained in:
Yitian4Debug 2023-12-04 13:33:55 -08:00 committed by GitHub
parent 5ca928efda
commit 7475a002b6
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml
View File

@ -1,7 +1,7 @@
<repack_design_constraints>
<pin_constraint pb_type="clb" pin="clk[0]" net="clk_i"/>
<pin_constraint pb_type="clb" pin="reset[0]" net="rst_i"/>
<ignore_net name="rst_i" pin="clb,I[0:11]"/>
<ignore_net name="rst_i" pin="clb.I[0:11]"/>
</repack_design_constraints>