From 7475a002b613c3a47ace2ce7f3cd7384a6a5f016 Mon Sep 17 00:00:00 2001
From: Yitian4Debug <97993988+Yitian4Debug@users.noreply.github.com>
Date: Mon, 4 Dec 2023 13:33:55 -0800
Subject: [PATCH] Update repack_design_constraints.xml by changing the
 separater between pb type and pin name

To avoid the syntax error in parsing design constraint file - since the regression system is not designed to capture such intended error.
---
 .../repack_ignore_nets/config/repack_design_constraints.xml     | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml
index d3fc31c4c..7c329b3e6 100644
--- a/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml
+++ b/openfpga_flow/tasks/fpga_bitstream/repack_ignore_nets/config/repack_design_constraints.xml
@@ -1,7 +1,7 @@
 <repack_design_constraints>
   <pin_constraint pb_type="clb" pin="clk[0]" net="clk_i"/>
   <pin_constraint pb_type="clb" pin="reset[0]" net="rst_i"/>
-  <ignore_net name="rst_i" pin="clb,I[0:11]"/>
+  <ignore_net name="rst_i" pin="clb.I[0:11]"/>
 
 </repack_design_constraints>